Merge remote-tracking branch 'tegra/for-next'

diff --combined drivers/clk/tegra/clk-dfll.c
index c4e3a52e225bcea0583d3eed0308a523b12ebec3,c56a5c7354847de37d17e0e9bd0aa1b2a9fe25da..86a307b17eb0a922acd2bac5ea16c6de16f5756e
--- 1/drivers/clk/tegra/clk-dfll.c
--- 2/drivers/clk/tegra/clk-dfll.c
+++ b/drivers/clk/tegra/clk-dfll.c
@@@ -468,56 -468,6 +468,6 @@@ static unsigned long dfll_scale_dvco_ra
        return (u64)dvco_rate * (scale_bits + 1) / DFLL_FREQ_REQ_SCALE_MAX;
  }
  
- /*
-  * Monitor control
-  */
- 
- /**
-  * dfll_calc_monitored_rate - convert DFLL_MONITOR_DATA_VAL rate into real freq
-  * @monitor_data: value read from the DFLL_MONITOR_DATA_VAL bitfield
-  * @ref_rate: DFLL reference clock rate
-  *
-  * Convert @monitor_data from DFLL_MONITOR_DATA_VAL units into cycles
-  * per second. Returns the converted value.
-  */
- static u64 dfll_calc_monitored_rate(u32 monitor_data,
-                                   unsigned long ref_rate)
- {
-       return monitor_data * (ref_rate / REF_CLK_CYC_PER_DVCO_SAMPLE);
- }
- 
- /**
-  * dfll_read_monitor_rate - return the DFLL's output rate from internal monitor
-  * @td: DFLL instance
-  *
-  * If the DFLL is enabled, return the last rate reported by the DFLL's
-  * internal monitoring hardware. This works in both open-loop and
-  * closed-loop mode, and takes the output scaler setting into account.
-  * Assumes that the monitor was programmed to monitor frequency before
-  * the sample period started. If the driver believes that the DFLL is
-  * currently uninitialized or disabled, it will return 0, since
-  * otherwise the DFLL monitor data register will return the last
-  * measured rate from when the DFLL was active.
-  */
- static u64 dfll_read_monitor_rate(struct tegra_dfll *td)
- {
-       u32 v, s;
-       u64 pre_scaler_rate, post_scaler_rate;
- 
-       if (!dfll_is_running(td))
-               return 0;
- 
-       v = dfll_readl(td, DFLL_MONITOR_DATA);
-       v = (v & DFLL_MONITOR_DATA_VAL_MASK) >> DFLL_MONITOR_DATA_VAL_SHIFT;
-       pre_scaler_rate = dfll_calc_monitored_rate(v, td->ref_rate);
- 
-       s = dfll_readl(td, DFLL_FREQ_REQ);
-       s = (s & DFLL_FREQ_REQ_SCALE_MASK) >> DFLL_FREQ_REQ_SCALE_SHIFT;
-       post_scaler_rate = dfll_scale_dvco_rate(s, pre_scaler_rate);
- 
-       return post_scaler_rate;
- }
- 
  /*
   * DFLL mode switching
   */
@@@ -682,17 -632,11 +632,17 @@@ static int find_lut_index_for_rate(stru
        struct dev_pm_opp *opp;
        int i, uv;
  
 +      rcu_read_lock();
 +
        opp = dev_pm_opp_find_freq_ceil(td->soc->dev, &rate);
 -      if (IS_ERR(opp))
 +      if (IS_ERR(opp)) {
 +              rcu_read_unlock();
                return PTR_ERR(opp);
 +      }
        uv = dev_pm_opp_get_voltage(opp);
  
 +      rcu_read_unlock();
 +
        for (i = 0; i < td->i2c_lut_size; i++) {
                if (regulator_list_voltage(td->vdd_reg, td->i2c_lut[i]) == uv)
                        return i;
@@@ -1006,24 -950,25 +956,25 @@@ static unsigned long dfll_clk_recalc_ra
        return td->last_unrounded_rate;
  }
  
- static long dfll_clk_round_rate(struct clk_hw *hw,
-                               unsigned long rate,
-                               unsigned long *parent_rate)
+ /* Must use determine_rate since it allows for rates exceeding 2^31-1 */
+ static int dfll_clk_determine_rate(struct clk_hw *hw,
+                                  struct clk_rate_request *clk_req)
  {
        struct tegra_dfll *td = clk_hw_to_dfll(hw);
        struct dfll_rate_req req;
        int ret;
  
-       ret = dfll_calculate_rate_request(td, &req, rate);
+       ret = dfll_calculate_rate_request(td, &req, clk_req->rate);
        if (ret)
                return ret;
  
        /*
-        * Don't return the rounded rate, since it doesn't really matter as
+        * Don't set the rounded rate, since it doesn't really matter as
         * the output rate will be voltage controlled anyway, and cpufreq
         * freaks out if any rounding happens.
         */
-       return rate;
+ 
+       return 0;
  }
  
  static int dfll_clk_set_rate(struct clk_hw *hw, unsigned long rate,
@@@ -1039,7 -984,7 +990,7 @@@ static const struct clk_ops dfll_clk_op
        .enable         = dfll_clk_enable,
        .disable        = dfll_clk_disable,
        .recalc_rate    = dfll_clk_recalc_rate,
-       .round_rate     = dfll_clk_round_rate,
+       .determine_rate = dfll_clk_determine_rate,
        .set_rate       = dfll_clk_set_rate,
  };
  
@@@ -1101,6 -1046,55 +1052,55 @@@ static void dfll_unregister_clk(struct 
   */
  
  #ifdef CONFIG_DEBUG_FS
+ /*
+  * Monitor control
+  */
+ 
+ /**
+  * dfll_calc_monitored_rate - convert DFLL_MONITOR_DATA_VAL rate into real freq
+  * @monitor_data: value read from the DFLL_MONITOR_DATA_VAL bitfield
+  * @ref_rate: DFLL reference clock rate
+  *
+  * Convert @monitor_data from DFLL_MONITOR_DATA_VAL units into cycles
+  * per second. Returns the converted value.
+  */
+ static u64 dfll_calc_monitored_rate(u32 monitor_data,
+                                   unsigned long ref_rate)
+ {
+       return monitor_data * (ref_rate / REF_CLK_CYC_PER_DVCO_SAMPLE);
+ }
+ 
+ /**
+  * dfll_read_monitor_rate - return the DFLL's output rate from internal monitor
+  * @td: DFLL instance
+  *
+  * If the DFLL is enabled, return the last rate reported by the DFLL's
+  * internal monitoring hardware. This works in both open-loop and
+  * closed-loop mode, and takes the output scaler setting into account.
+  * Assumes that the monitor was programmed to monitor frequency before
+  * the sample period started. If the driver believes that the DFLL is
+  * currently uninitialized or disabled, it will return 0, since
+  * otherwise the DFLL monitor data register will return the last
+  * measured rate from when the DFLL was active.
+  */
+ static u64 dfll_read_monitor_rate(struct tegra_dfll *td)
+ {
+       u32 v, s;
+       u64 pre_scaler_rate, post_scaler_rate;
+ 
+       if (!dfll_is_running(td))
+               return 0;
+ 
+       v = dfll_readl(td, DFLL_MONITOR_DATA);
+       v = (v & DFLL_MONITOR_DATA_VAL_MASK) >> DFLL_MONITOR_DATA_VAL_SHIFT;
+       pre_scaler_rate = dfll_calc_monitored_rate(v, td->ref_rate);
+ 
+       s = dfll_readl(td, DFLL_FREQ_REQ);
+       s = (s & DFLL_FREQ_REQ_SCALE_MASK) >> DFLL_FREQ_REQ_SCALE_SHIFT;
+       post_scaler_rate = dfll_scale_dvco_rate(s, pre_scaler_rate);
+ 
+       return post_scaler_rate;
+ }
  
  static int attr_enable_get(void *data, u64 *val)
  {