ARM: sunxi: add PLL5 and PLL6 support

This commit adds PLL5 and PLL6 nodes to the sun4i, sun5i and sun7i
device trees.

Signed-off-by: Emilio López <emilio@elopez.com.ar>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>

diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index a6c1caeae6a0226d8ff1943383e8ad726c5920c0..5e2fc45f3c1aebd4479956ba52a1230883d13cf2 100644 (file)
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -73,6 +73,22 @@
                        clocks = <&osc24M>;
                };
 
+               pll5: pll5@01c20020 {
+                       #clock-cells = <1>;
+                       compatible = "allwinner,sun4i-pll5-clk";
+                       reg = <0x01c20020 0x4>;
+                       clocks = <&osc24M>;
+                       clock-output-names = "pll5_ddr", "pll5_other";
+               };
+
+               pll6: pll6@01c20028 {
+                       #clock-cells = <1>;
+                       compatible = "allwinner,sun4i-pll6-clk";
+                       reg = <0x01c20028 0x4>;
+                       clocks = <&osc24M>;
+                       clock-output-names = "pll6_sata", "pll6_other", "pll6";
+               };
+
                /* dummy is 200M */
                cpu: cpu@01c20054 {
                        #clock-cells = <0>;
@@ -138,12 +154,11 @@
                                "apb0_ir1", "apb0_keypad";
                };
 
-               /* dummy is pll62 */
                apb1_mux: apb1_mux@01c20058 {
                        #clock-cells = <0>;
                        compatible = "allwinner,sun4i-apb1-mux-clk";
                        reg = <0x01c20058 0x4>;
-                       clocks = <&osc24M>, <&dummy>, <&osc32k>;
+                       clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
                };
 
                apb1: apb1@01c20058 {

diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
index c3f4eed3691bb6268f3be343247b8257fb0bbb20..b29412ac98dfa507111a8eadfdff17545d56397f 100644 (file)
--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
@@ -70,6 +70,22 @@
                        clocks = <&osc24M>;
                };
 
+               pll5: pll5@01c20020 {
+                       #clock-cells = <1>;
+                       compatible = "allwinner,sun4i-pll5-clk";
+                       reg = <0x01c20020 0x4>;
+                       clocks = <&osc24M>;
+                       clock-output-names = "pll5_ddr", "pll5_other";
+               };
+
+               pll6: pll6@01c20028 {
+                       #clock-cells = <1>;
+                       compatible = "allwinner,sun4i-pll6-clk";
+                       reg = <0x01c20028 0x4>;
+                       clocks = <&osc24M>;
+                       clock-output-names = "pll6_sata", "pll6_other", "pll6";
+               };
+
                /* dummy is 200M */
                cpu: cpu@01c20054 {
                        #clock-cells = <0>;
@@ -130,12 +146,11 @@
                                "apb0_ir", "apb0_keypad";
                };
 
-               /* dummy is pll62 */
                apb1_mux: apb1_mux@01c20058 {
                        #clock-cells = <0>;
                        compatible = "allwinner,sun4i-apb1-mux-clk";
                        reg = <0x01c20058 0x4>;
-                       clocks = <&osc24M>, <&dummy>, <&osc32k>;
+                       clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
                };
 
                apb1: apb1@01c20058 {

diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index 8c4a9c3c069c79c61668d98150ce349050194545..cded3c7969743f7a31755d52eb1cfefbfd479031 100644 (file)
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -74,6 +74,22 @@
                        clocks = <&osc24M>;
                };
 
+               pll5: pll5@01c20020 {
+                       #clock-cells = <1>;
+                       compatible = "allwinner,sun4i-pll5-clk";
+                       reg = <0x01c20020 0x4>;
+                       clocks = <&osc24M>;
+                       clock-output-names = "pll5_ddr", "pll5_other";
+               };
+
+               pll6: pll6@01c20028 {
+                       #clock-cells = <1>;
+                       compatible = "allwinner,sun4i-pll6-clk";
+                       reg = <0x01c20028 0x4>;
+                       clocks = <&osc24M>;
+                       clock-output-names = "pll6_sata", "pll6_other", "pll6";
+               };
+
                /* dummy is 200M */
                cpu: cpu@01c20054 {
                        #clock-cells = <0>;
@@ -132,12 +148,11 @@
                        clock-output-names = "apb0_codec", "apb0_pio", "apb0_ir";
                };
 
-               /* dummy is pll6 */
                apb1_mux: apb1_mux@01c20058 {
                        #clock-cells = <0>;
                        compatible = "allwinner,sun4i-apb1-mux-clk";
                        reg = <0x01c20058 0x4>;
-                       clocks = <&osc24M>, <&dummy>, <&osc32k>;
+                       clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
                };
 
                apb1: apb1@01c20058 {

diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index e4a5d37a12f8164b21871d6281100d73b1a6e153..a6cd039d5a0c5a850f3609e1c8e5b005e3244421 100644 (file)
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -69,23 +69,27 @@
                        clocks = <&osc24M>;
                };
 
-               /*
-                * This is a dummy clock, to be used as placeholder on
-                * other mux clocks when a specific parent clock is not
-                * yet implemented. It should be dropped when the driver
-                * is complete.
-                */
-               pll6: pll6 {
-                       #clock-cells = <0>;
-                       compatible = "fixed-clock";
-                       clock-frequency = <0>;
+               pll5: pll5@01c20020 {
+                       #clock-cells = <1>;
+                       compatible = "allwinner,sun4i-pll5-clk";
+                       reg = <0x01c20020 0x4>;
+                       clocks = <&osc24M>;
+                       clock-output-names = "pll5_ddr", "pll5_other";
+               };
+
+               pll6: pll6@01c20028 {
+                       #clock-cells = <1>;
+                       compatible = "allwinner,sun4i-pll6-clk";
+                       reg = <0x01c20028 0x4>;
+                       clocks = <&osc24M>;
+                       clock-output-names = "pll6_sata", "pll6_other", "pll6";
                };
 
                cpu: cpu@01c20054 {
                        #clock-cells = <0>;
                        compatible = "allwinner,sun4i-cpu-clk";
                        reg = <0x01c20054 0x4>;
-                       clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6>;
+                       clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>;
                };
 
                axi: axi@01c20054 {
@@ -144,7 +148,7 @@
                        #clock-cells = <0>;
                        compatible = "allwinner,sun4i-apb1-mux-clk";
                        reg = <0x01c20058 0x4>;
-                       clocks = <&osc24M>, <&pll6>, <&osc32k>;
+                       clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
                };
 
                apb1: apb1@01c20058 {