]> git.kernelconcepts.de Git - karo-tx-linux.git/commitdiff
ARM: mvebu: use DT properties to fine-tune the L2 configuration
authorThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Thu, 11 Jun 2015 11:51:12 +0000 (13:51 +0200)
committerGregory CLEMENT <gregory.clement@free-electrons.com>
Thu, 9 Jul 2015 12:25:28 +0000 (14:25 +0200)
In order to optimize the L2 cache performance, this commit adjusts the
configuration of the L2 on the Cortex-A9 based Marvell EBU processors
(Armada 375, 38x and 39x), using the appropriate DT properties.

We enable double linefill, incr double linefill, data prefetch and
disable double linefill on wrap. This matches the configuration that
was fine tuned in the Marvell BSP.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
arch/arm/boot/dts/armada-375.dtsi
arch/arm/boot/dts/armada-38x.dtsi
arch/arm/boot/dts/armada-39x.dtsi

index 67a0ab0f71e029bfa36ffcccbd34ded49c80b164..e9a381741ce12e2eba5108aebf9517e6a4a1aa6c 100644 (file)
                                reg = <0x8000 0x1000>;
                                cache-unified;
                                cache-level = <2>;
+                               arm,double-linefill-incr = <1>;
+                               arm,double-linefill-wrap = <0>;
+                               arm,double-linefill = <1>;
+                               prefetch-data = <1>;
                        };
 
                        scu@c000 {
index 1230bfd01a7e4373571154b1c949550e91b2778e..f9f2347d9995a824cb53a7ceb7bf3cf907e85685 100644 (file)
                                reg = <0x8000 0x1000>;
                                cache-unified;
                                cache-level = <2>;
+                               arm,double-linefill-incr = <1>;
+                               arm,double-linefill-wrap = <0>;
+                               arm,double-linefill = <1>;
+                               prefetch-data = <1>;
                        };
 
                        scu@c000 {
index 619b79043eee3f9721424f1c2932e26bcb7897ca..dc6efd386dbcb00db09c5e8171f15f83beb1dd09 100644 (file)
                                reg = <0x8000 0x1000>;
                                cache-unified;
                                cache-level = <2>;
+                               arm,double-linefill-incr = <1>;
+                               arm,double-linefill-wrap = <0>;
+                               arm,double-linefill = <1>;
+                               prefetch-data = <1>;
                        };
 
                        scu@c000 {