1 //==========================================================================
7 //==========================================================================
8 //####ECOSGPLCOPYRIGHTBEGIN####
9 // -------------------------------------------
10 // This file is part of eCos, the Embedded Configurable Operating System.
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38 // -------------------------------------------
39 //####ECOSGPLCOPYRIGHTEND####
40 //==========================================================================
41 //#####DESCRIPTIONBEGIN####
44 // Contributors: gthomas, jskov
45 // Grant Edwards <grante@visi.com>
50 //####DESCRIPTIONEND####
52 //========================================================================*/
54 #ifndef KS32C5000_ETHER_H
55 #define KS32C5000_ETHER_H
57 // Tx Frame Descriptor's control bits -- Refer the KS32C5000 Manual Page 7-15
58 #define FRM_OWNERSHIP_BDMA 0x80000000 // 0:CPU, 1:BDMA
59 #define FRM_OWNERSHIP_CPU 0x7fffffff // 0:CPU, 1:BDMA
61 #define TXFDCON_PADDING_MODE 0x00
62 #define TXFDCON_NO_PADDING_MODE 0x01
63 #define TXFDCON_NO_CRC_MODE 0x02
64 #define TXFDCON_CRC_MODE 0x00
65 #define TXFDCON_MAC_TX_INT_EN 0x04
66 #define TXFDCON_LITTLE_ENDIAN 0x08
67 #define TXFDCON_BIG_ENDIAN 0x00
68 #define TXFDCON_SRC_ADDR_DEC 0x00
69 #define TXFDCON_SRC_ADDR_INC 0x10
70 #define TXFDCON_WIDGET_ALIGN00 0x00 // No Invalid bytes
71 #define TXFDCON_WIDGET_ALIGN01 0x01 // 1 Invalid byte
72 #define TXFDCON_WIDGET_ALIGN10 0x10 // 2 Invalid bytes
73 #define TXFDCON_WIDGET_ALIGN11 0x11 // 3 Invalid bytes
75 // Tx Frame descriptor's Status
76 #define TXFDSTAT_EX_COLL 0x0010 // Excessive Collision
77 #define TXFDSTAT_DEFFER 0x0020 // Transmit deffered
78 #define TXFDSTAT_PAUSED 0x0040 // Paused : holding data transmission DMA to MAC
79 #define TXFDSTAT_INT_TX 0x0080 // Interrupt on Transmit
80 #define TXFDSTAT_UNDER 0x0100 // Underrun */
81 #define TXFDSTAT_DEFER 0x0200 // Mac defers for Max_DEFERRAL:=0.32768ms
82 // for 100Mbits/s, := 3.2768ms for 10Mbits/s
83 #define TXFDSTAT_NCARR 0x0400 // No Carrier sense is detected during the
84 // entire transmission of a packet from SFD
86 #define TXFDSTAT_SQ_ERR 0x0800 // fake collision signal didn't come from
88 #define TXFDSTAT_LATE_COLL 0x1000 // Late collision
89 #define TXFDSTAT_PAR 0x2000 // Transmit Parity Error
90 #define TXFDSTAT_COMP 0x4000 // MAC transmit or discards one packet
91 #define TXFDSTAT_HALTED 0x8000 // Transmission was halted by clearing MACTXCON_TX_EN..
93 // Rx Frame descriptor's Status
94 #define RXFDSTAT_OV_MAX 0x0008 // Over Maximum Size
95 #define RXFDSTAT_CTL_RECD 0x0020 // set if packet received is a
97 #define RXFDSTAT_INT_RX 0x0040 // Interrupt on Receive
98 #define RXFDSTAT_10STAT 0x0080 // set if packet was received via the
99 // 10bits interface reset if packet
100 // was received via MII
101 #define RXFDSTAT_ALIGN_ERR 0x0100 // Alignment Error
102 #define RXFDSTAT_CRC_ERR 0x0200 // CRC error
103 #define RXFDSTAT_OVERFLOW 0x0400 // MAC receive FIFO was full when it
104 // needed to store a received byte
106 #define RXFDSTAT_LONG_ERR 0x0800 // received a frame longer than 1518bytes
107 #define RXFDSTAT_PAR 0x2000 // MAC receive FIFO has detected a parity error
108 #define RXFDSTAT_GOOD 0x4000 // successfully received a packet with no errors
109 #define RXFDSTAT_HALTED 0x8000 // Transmission was halted by clearing MACTXCON_TX_EN...
111 // BDMARXCON : 0x9004
112 // Buffered DMA Receiver Control Register
113 #define BDMARXCON_BRST 0x00001F // BDMA Rx Burst Size * BDMARXCON_BRST
114 #define BDMARXCON_STP_SKP 0x00020 // BDMA Rx Stop/Skip Frame or Interrupt(=1)
115 #define BDMARXCON_MA_INC 0x00040 // BDMA Rx Memory Address Inc/Dec
116 #define BDMARXCON_DIE 0x00080 // BDMA Rx Every Received Frame Interrupt Enable
117 #define BDMARXCON_NLIE 0x00100 // BDMA Rx NULL List Interrupt Enable
118 #define BDMARXCON_NOIE 0x00200 // BDMA Rx Not Owner Interrupt Enable
119 #define BDMARXCON_MSOIE 0x00400 // BDMA Rx Maximum Size over Interrupr Enable
120 #define BDMARXCON_LITTLE 0x00800 // BDMA Rx Big/Little Endian
121 #define BDMARXCON_BIG 0x00000 // BDMA Rx Big/Little Endian
122 #define BDMARXCON_WA00 0x00000 // BDMA Rx Word Alignment- no invalid byte
123 #define BDMARXCON_WA01 0x01000 // BDMA Rx Word Alignment- one invalid byte
124 #define BDMARXCON_WA10 0x02000 // BDMA Rx Word Alignment- two invalid byte
125 #define BDMARXCON_WA11 0x03000 // BDMA Rx Word Alignment- three invalid byte
126 #define BDMARXCON_EN 0x04000 // BDMA Rx Enable
127 #define BDMARXCON_RESET 0x08000 // BDMA Rx Reset
128 #define BDMARXCON_RX_EMPT 0x10000 // BDMA Rx Buffer empty interrupt
129 #define BDMARXCON_EARLY 0x20000 // BDMA Rx Early notify Interrupt
131 // BDMATXCON : 0x9000
132 // Buffered DMA Trasmit Control Register
133 #define BDMATXCON_BRST 0x000F // BDMA Tx Burst Size = 16
134 #define BDMATXCON_STP_SKP 0x0020 // BDMA Tx Stop/Skip Frame or Interrupt in case
135 // of not Owner the current frame
136 #define BDMATXCON_CPIE 0x0080 // BDMA Tx Complete to send control
138 #define BDMATXCON_NOIE 0x0200 // BDMA Tx Buffer Not Owner
139 #define BDMATXCON_TX_EMPTY 0x0400 // BDMA Tx Buffer Empty Interrupt
140 #define BDMATXCON_TX_NOIE 0x0200 // BDMA Tx not owner (queue empty)
141 #define BDMATXCON_TX_NULL 0x0100 // BDMA dscr pointer null
143 // BDMA Tx buffer can be moved to the MAC Tx IO
144 // when the new frame comes in.
145 #define BDMATXCON_MSL000 0x00000 // No wait to fill the BDMA
146 #define BDMATXCON_MSL001 0x00800 // wait to fill 1/8 of the BDMA
147 #define BDMATXCON_MSL010 0x01000 // wait to fill 2/8 of the BDMA
148 #define BDMATXCON_MSL011 0x01800 // wait to fill 3/8 of the BDMA
149 #define BDMATXCON_MSL100 0x02000 // wait to fill 4/8 of the BDMA
150 #define BDMATXCON_MSL101 0x02800 // wait to fill 5/8 of the BDMA
151 #define BDMATXCON_MSL110 0x03000 // wait to fill 6/8 of the BDMA
152 #define BDMATXCON_MSL111 0x03800 // wait to fill 7/8 of the BDMA
153 #define BDMATXCON_EN 0x04000 // BDMA Tx Enable
154 #define BDMATXCON_RESET 0x08000 // BDMA Rx Reset
157 // Buffered DMA Status Register
158 #define BDMASTAT_RX_RDF 0x00001 // BDMA Rx Done Every Received Frame
159 #define BDMASTAT_RX_NL 0x00002 // BDMA Rx NULL List
160 #define BDMASTAT_RX_NO 0x00004 // BDMA Rx Not Owner
161 #define BDMASTAT_RX_MSO 0x00008 // BDMA Rx Maximum Size Over
162 #define BDMASTAT_RX_EMPTY 0x00010 // BDMA Rx Buffer Empty
163 #define BDMASTAT_RX_SEARLY 0x00020 // Early Notify
164 #define BDMASTAT_RX_FRF 0x00080 // One more frame data in BDMA receive buffer
165 #define BDMASTAT_TX_CCP 0x10000 // BDMA Tx Complete to send Control Packet
166 #define BDMASTAT_TX_NL 0x20000 // BDMA Tx Null List
167 #define BDMASTAT_TX_NO 0x40000 // BDMA Tx Not Owner
168 #define BDMASTAT_TX_EMPTY 0x100000// BDMA Tx Buffer Empty
171 // MAC Control Register
172 #define MACON_HALT_REG 0x0001 // stop transmission and reception
173 // after completion of ant current packets
174 #define MACON_HALT_IMM 0x0002 // Stop transmission and reception immediately
175 #define MACON_SW_RESET 0x0004 // reset all Ethernet controller state machines
177 #define MACON_FULL_DUP 0x0008 // allow transmission to begin while reception
179 #define MACON_MAC_LOOP 0x0010 // MAC loopback
180 #define MACON_CONN_M00 0x0000 // Automatic-default
181 #define MACON_CONN_M01 0x0020 // Force 10Mbits endec
182 #define MACON_CONN_M10 0x0040 // Force MII (rate determined by MII clock
183 #define MACON_LOOP10 0x0080 // Loop 10Mbps
184 #define MACON_MISS_ROLL 0x0400 // Missed error counter rolled over
185 #define MACON_EN_MISS_ROLL 0x2000 // Interrupt when missed error counter rolls
187 #define MACON_LINK10 0x8000 // Link status 10Mbps
190 // CAM control register
191 #define CAMCON_STATION_ACC 0x0001 // Accept any packet with a unicast station
193 #define CAMCON_GROUP_ACC 0x0002 // Accept any packet with multicast-group
195 #define CAMCON_BROAD_ACC 0x0004 // Accept any packet with a broadcast station
197 #define CAMCON_NEG_CAM 0x0008 // 0: Accept packets CAM recognizes,
199 // 1: reject packets CAM recognizes,
201 #define CAMCON_COMP_EN 0x0010 // Compare Enable mode
204 // Transmit Control Register
205 #define MACTXCON_TX_EN 0x0001 // transmit Enable
206 #define MACTXCON_TX_HALT 0x0002 // Transmit Halt Request
207 #define MACTXCON_NO_PAD 0x0004 // suppress Padding
208 #define MACTXCON_NO_CRC 0x0008 // Suppress CRC
209 #define MACTXCON_FBACK 0x0010 // Fast Back-off
210 #define MACTXCON_NO_DEF 0x0020 // Disable the defer counter
211 #define MACTXCON_SD_PAUSE 0x0040 // Send Pause
212 #define MACTXCON_MII10_EN 0x0080 // MII 10Mbps mode enable
213 #define MACTXCON_EN_UNDER 0x0100 // Enable Underrun
214 #define MACTXCON_EN_DEFER 0x0200 // Enable Deferral
215 #define MACTXCON_EN_NCARR 0x0400 // Enable No Carrier
216 #define MACTXCON_EN_EXCOLL 0x0800 // interrupt if 16 collision occur
217 // in the same packet
218 #define MACTXCON_EN_LATE_COLL 0x1000 // interrupt if collision occurs after
219 // 512 bit times(64 bytes times)
220 #define MACTXCON_ENTX_PAR 0x2000 // interrupt if the MAC transmit FIFO
221 // has a parity error
222 #define MACTXCON_EN_COMP 0x4000 // interrupt when the MAC transmits or
223 // discards one packet
224 // MACTXSTAT : 0xa00c
225 // Transmit Status Register
226 #define MACTXSTAT_EX_COLL 0x0010 // Excessive collision
227 #define MACTXSTAT_DEFFERED 0x0020 // set if 16 collisions occur for same packet
228 #define MACTXSTAT_PAUSED 0x0040 // packet waited because of pause during
230 #define MACTXSTAT_INT_TX 0x0080 // set if transmission of packet causes an
231 // interrupt condiftion
232 #define MACTXSTAT_UNDER 0x0100 // MAC transmit FIFO becomes empty during
234 #define MACTXSTAT_DEFER 0x0200 // MAC defers for MAC deferral
235 #define MACTXSTAT_NCARR 0x0400 // No carrier sense detected during the
236 // transmission of a packet
237 #define MACTXSTAT_SIG_QUAL 0x0800 // Signal Quality Error
238 #define MACTXSTAT_LATE_COLL 0x1000 // a collision occures after 512 bit times
239 #define MACTXSTAT_PAR 0x2000 // MAC transmit FIFO has detected a parity error
240 #define MACTXSTAT_COMP 0x4000 // MAC transmit or discards one packet
241 #define MACTXSTAT_HALTED 0x8000 // Transmission was halted by clearing
242 // MACTXCON_TX_EN or Halt immedite
244 // Receive Control Register
245 #define MACRXCON_RX_EN 0x0001
246 #define MACRXCON_HALT 0x0002
247 #define MACRXCON_LONG_EN 0x0004
248 #define MACRXCON_SHORT_EN 0x0008
249 #define MACRXCON_STRIP_CRC 0x0010
250 #define MACRXCON_PASS_CTL 0x0020
251 #define MACRXCON_IGNORE_CRC 0x0040
252 #define MACRXCON_EN_ALIGN 0x0100
253 #define MACRXCON_EN_CRC_ERR 0x0200
254 #define MACRXCON_EN_OVER 0x0400
255 #define MACRXCON_EN_LONG_ERR 0x0800
256 #define MACRXCON_EN_RX_PAR 0x2000
257 #define MACRXCON_EN_GOOD 0x4000
259 // MACRXSTAT : 0xa014
260 // Receive Status Register
261 #define MACRXSTAT_CTL_RECD 0x0020
262 #define MACRXSTAT_INT_RX 0x0040
263 #define MACRXSTAT_10STAT 0x0080
264 #define MACRXSTAT_ALLIGN_ERR 0x0100
265 #define MACRXSTAT_CRC_ERR 0x0200
266 #define MACRXSTAT_OVERFLOW 0x0400
267 #define MACRXSTAT_LONG_ERR 0x0800
268 #define MACRXSTAT_PAR 0x2000
269 #define MACRXSTAT_GOOD 0x4000
270 #define MACRXSTAT_HALTED 0x8000