1 //==========================================================================
7 //==========================================================================
8 //####ECOSGPLCOPYRIGHTBEGIN####
9 // -------------------------------------------
10 // This file is part of eCos, the Embedded Configurable Operating System.
11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
13 // eCos is free software; you can redistribute it and/or modify it under
14 // the terms of the GNU General Public License as published by the Free
15 // Software Foundation; either version 2 or (at your option) any later version.
17 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
18 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
19 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
22 // You should have received a copy of the GNU General Public License along
23 // with eCos; if not, write to the Free Software Foundation, Inc.,
24 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
26 // As a special exception, if other files instantiate templates or use macros
27 // or inline functions from this file, or you compile this file and link it
28 // with other works to produce a work based on this file, this file does not
29 // by itself cause the resulting work to be covered by the GNU General Public
30 // License. However the source code for this file must still be made available
31 // in accordance with section (3) of the GNU General Public License.
33 // This exception does not invalidate any other reasons why a work based on
34 // this file might be covered by the GNU General Public License.
36 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
37 // at http://sources.redhat.com/ecos/ecos-license/
38 // -------------------------------------------
39 //####ECOSGPLCOPYRIGHTEND####
40 //==========================================================================
41 //#####DESCRIPTIONBEGIN####
44 // Contributors: gthomas, jskov
45 // Grant Edwards <grante@visi.com>
50 //####DESCRIPTIONEND####
52 //========================================================================*/
54 /*------------------------------------------------------------------------
56 purpose : This is the header file that will define all the
57 registers for the ks5000 processor. It will contain
58 the addresses for the registers and some values for
60 ========================================================================*/
61 #ifndef _KS5000_REGS_H_
62 #define _KS5000_REGS_H_
66 #define BD_LAN_STOP {}
67 #define DEBUG 0 /* DEBUG mode */
69 #define VPint(a) (*((volatile unsigned int*)(a)))
70 #define VPshort(a) (*((volatile unsigned short int*)(a)))
71 #define VPchar(a) (*((volatile unsigned char*)(a)))
73 #define Base_Addr 0x7ff0000
75 #define INTADDR (Reset_Addr+0x20)
76 #define SPSTR (VPint(Base_Addr))
78 // System Manager Register
79 #define SYSCFG (VPint(Base_Addr+0x0000))
80 #define CLKCON (VPint(Base_Addr+0x3000))
81 #define EXTACON0 (VPint(Base_Addr+0x3008))
82 #define EXTACON1 (VPint(Base_Addr+0x300c))
83 #define EXTDBWTH (VPint(Base_Addr+0x3010))
84 #define ROMCON0 (VPint(Base_Addr+0x3014))
85 #define ROMCON1 (VPint(Base_Addr+0x3018))
86 #define ROMCON2 (VPint(Base_Addr+0x301c))
87 #define ROMCON3 (VPint(Base_Addr+0x3020))
88 #define ROMCON4 (VPint(Base_Addr+0x3024))
89 #define ROMCON5 (VPint(Base_Addr+0x3028))
90 #define DRAMCON0 (VPint(Base_Addr+0x302c))
91 #define DRAMCON1 (VPint(Base_Addr+0x3030))
92 #define DRAMCON2 (VPint(Base_Addr+0x3034))
93 #define DRAMCON3 (VPint(Base_Addr+0x3038))
94 #define REFEXTCON (VPint(Base_Addr+0x303c))
96 // Ethernet BDMA Register
97 #define BDMATXCON (VPint(Base_Addr+0x9000))
98 #define BDMARXCON (VPint(Base_Addr+0x9004))
99 #define BDMATXPTR (VPint(Base_Addr+0x9008))
100 #define BDMARXPTR (VPint(Base_Addr+0x900c))
101 #define BDMARXLSZ (VPint(Base_Addr+0x9010))
102 #define BDMASTAT (VPint(Base_Addr+0x9014))
104 #define CAM_BASE (VPint(Base_Addr+0x9100))
105 #define BDMATXBUF (VPint(Base_Addr+0x9200))
106 #define BDMARXBUF (VPint(Base_Addr+0x9800))
107 #define CAM_BaseAddr (Base_Addr+0x9100)
109 // Ethernet MAC Register
110 #define MACCON (VPint(Base_Addr+0xa000))
111 #define CAMCON (VPint(Base_Addr+0xa004))
112 #define MACTXCON (VPint(Base_Addr+0xa008))
113 #define MACTXSTAT (VPint(Base_Addr+0xa00c))
114 #define MACRXCON (VPint(Base_Addr+0xa010))
115 #define MACRXSTAT (VPint(Base_Addr+0xa014))
116 #define STADATA (VPint(Base_Addr+0xa018))
117 #define STACON (VPint(Base_Addr+0xa01c))
118 #define CAMEN (VPint(Base_Addr+0xa028))
119 #define EMISSCNT (VPint(Base_Addr+0xa03c))
120 #define EPZCNT (VPint(Base_Addr+0xa040))
121 #define ERMPZCNT (VPint(Base_Addr+0xa044))
122 #define ETXSTAT (VPint(Base_Addr+0xa048))
123 #define MACRXDESTR (VPint(Base_Addr+0xa064))
124 #define MACRXSTATEM (VPint(Base_Addr+0xa090))
127 #define HCON0A (VPint(Base_Addr+0x7000))
128 #define HCON1A (VPint(Base_Addr+0x7004))
129 #define HSTATA (VPint(Base_Addr+0x7008))
130 #define HINTENA (VPint(Base_Addr+0x700c))
131 #define HTXFIFOCA (VPint(Base_Addr+0x7010))
132 #define HTXFIFOTA (VPint(Base_Addr+0x7014))
133 #define HRXFIFOA (VPint(Base_Addr+0x7018))
134 #define HSADRA (VPint(Base_Addr+0x701c))
135 #define HBRGTCA (VPint(Base_Addr+0x7020))
136 #define HPRMBA (VPint(Base_Addr+0x7024))
137 #define HDMATXMAA (VPint(Base_Addr+0x7028))
138 #define HDMARXMAA (VPint(Base_Addr+0x702c))
139 #define HDMATXCNTA (VPint(Base_Addr+0x7030))
140 #define HDMARXCNTA (VPint(Base_Addr+0x7034))
141 #define HDMARXBCNTA (VPint(Base_Addr+0x7038))
144 #define HCON0B (VPint(Base_Addr+0x8000))
145 #define HCON1B (VPint(Base_Addr+0x8004))
146 #define HSTATB (VPint(Base_Addr+0x8008))
147 #define HINTENB (VPint(Base_Addr+0x800c))
148 #define HTXFIFOCB (VPint(Base_Addr+0x8010))
149 #define HTXFIFOTB (VPint(Base_Addr+0x8014))
150 #define HRXFIFOB (VPint(Base_Addr+0x8018))
151 #define HSADRB (VPint(Base_Addr+0x801c))
152 #define HBRGTCB (VPint(Base_Addr+0x8020))
153 #define HPRMBB (VPint(Base_Addr+0x8024))
154 #define HDMATXMAB (VPint(Base_Addr+0x8028))
155 #define HDMARXMAB (VPint(Base_Addr+0x802c))
156 #define HDMATXCNTB (VPint(Base_Addr+0x8030))
157 #define HDMARXCNTB (VPint(Base_Addr+0x8034))
158 #define HDMARXBCNTB (VPint(Base_Addr+0x8038))
161 #define IICCON (VPint(Base_Addr+0xf000))
162 #define IICBUF (VPint(Base_Addr+0xf004))
163 #define IICPS (VPint(Base_Addr+0xf008))
164 #define IICCOUNT (VPint(Base_Addr+0xf00c))
167 #define GDMACON0 (VPint(Base_Addr+0xb000))
168 #define GDMASRC0 (VPint(Base_Addr+0xb004))
169 #define GDMADST0 (VPint(Base_Addr+0xb008))
170 #define GDMACNT0 (VPint(Base_Addr+0xb00c))
173 #define GDMACON1 (VPint(Base_Addr+0xc000))
174 #define GDMASRC1 (VPint(Base_Addr+0xc004))
175 #define GDMADST1 (VPint(Base_Addr+0xc008))
176 #define GDMACNT1 (VPint(Base_Addr+0xc00c))
179 #define UART0_LCR (VPint(Base_Addr+0xd000)) // line control register
180 #define UART0_CTRL (VPint(Base_Addr+0xd004)) // uart control register
181 #define UART0_LST (VPint(Base_Addr+0xd008)) // line status register
182 #define UART0_THR (VPint(Base_Addr+0xd00c)) // transmit holding reg.
183 #define UART0_RDR (VPint(Base_Addr+0xd010)) // receive data register
184 #define UART0_BRD (VPint(Base_Addr+0xd014)) // baud rate divisor
187 #define UART1_LCR (VPint(Base_Addr+0xe000)) // line control register
188 #define UART1_CTRL (VPint(Base_Addr+0xe004)) // uart control register
189 #define UART1_LST (VPint(Base_Addr+0xe008)) // line status register
190 #define UART1_THR (VPint(Base_Addr+0xe00c)) // transmit holding reg.
191 #define UART1_RDR (VPint(Base_Addr+0xe010)) // receive data register
192 #define UART1_BRD (VPint(Base_Addr+0xe014)) // baud rate divisor
195 #define TMOD (VPint(Base_Addr+0x6000))
196 #define TDATA0 (VPint(Base_Addr+0x6004))
197 #define TDATA1 (VPint(Base_Addr+0x6008))
198 #define TCNT0 (VPint(Base_Addr+0x600c))
199 #define TCNT1 (VPint(Base_Addr+0x6010))
201 // Timer Mode Register
202 #define TM0_RUN 0x01 /* Timer 0 enable */
203 #define TM0_TOGGLE 0x02 /* 0, interval mode */
204 #define TM0_OUT_1 0x04 /* Timer 0 Initial TOUT0 value */
205 #define TM1_RUN 0x08 /* Timer 1 enable */
206 #define TM1_TOGGLE 0x10 /* 0, interval mode */
207 #define TM1_OUT_1 0x20 /* Timer 0 Initial TOUT0 value */
209 // I/O Port Interface
210 #define IOPMOD (VPint(Base_Addr+0x5000))
211 #define IOPCON (VPint(Base_Addr+0x5004))
212 #define IOPDATA (VPint(Base_Addr+0x5008))
214 // Interrupt Controller Register
215 #define INTMODE (VPint(Base_Addr+0x4000))
216 #define INTPEND (VPint(Base_Addr+0x4004))
217 #define INTMASK (VPint(Base_Addr+0x4008))
219 #define INTPRI0 (VPint(Base_Addr+0x400c))
220 #define INTPRI1 (VPint(Base_Addr+0x4010))
221 #define INTPRI2 (VPint(Base_Addr+0x4014))
222 #define INTPRI3 (VPint(Base_Addr+0x4018))
223 #define INTPRI4 (VPint(Base_Addr+0x401c))
224 #define INTPRI5 (VPint(Base_Addr+0x4020))
225 #define INTOFFSET (VPint(Base_Addr+0x4024))