1 //==========================================================================
3 // devs_eth_arm_board.inl
5 // Board ethernet I/O definitions.
7 //==========================================================================
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38 // -------------------------------------------
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40 //===========================================================================
42 #include <cyg/hal/hal_intr.h> // CYGNUM_HAL_INTERRUPT_ETHR
43 #include <cyg/hal/hal_if.h>
46 #include <pkgconf/redboot.h>
47 #ifdef CYGSEM_REDBOOT_FLASH_CONFIG
49 #include <flash_config.h>
53 extern unsigned int sys_ver;
57 #ifdef CYGPKG_DEVS_ETH_ARM_MXCBOARD_ETH0
59 #if defined(CYGPKG_REDBOOT) && defined(CYGSEM_REDBOOT_FLASH_CONFIG)
60 RedBoot_config_option("Set " CYGDAT_DEVS_ETH_ARM_MXCBOARD_ETH0_NAME " network hardware address [MAC]",
65 RedBoot_config_option(CYGDAT_DEVS_ETH_ARM_MXCBOARD_ETH0_NAME " network hardware address [MAC]",
70 #endif // CYGPKG_REDBOOT && CYGSEM_REDBOOT_FLASH_CONFIG
72 #ifdef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
73 // Note that this section *is* active in an application, outside RedBoot,
74 // where the above section is not included.
76 #include <cyg/hal/hal_if.h>
79 #define CONFIG_ESA (6)
82 #define CONFIG_BOOL (1)
85 cyg_bool _board_provide_eth0_esa(struct cs8900a_priv_data* cpd)
89 ok = CYGACC_CALL_IF_FLASH_CFG_OP( CYGNUM_CALL_IF_FLASH_CFG_GET,
90 "eth0_esa", &set_esa, CONFIG_BOOL);
92 ok = CYGACC_CALL_IF_FLASH_CFG_OP( CYGNUM_CALL_IF_FLASH_CFG_GET,
93 "eth0_esa_data", cpd->esa, CONFIG_ESA);
99 #endif // CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
102 // ------------------------------------------------------------------------
103 // EEPROM access functions
105 #define PP_ECR 0x0040
106 #define PP_EE_READ_CMD 0x0200
107 #define PP_EE_WRITE_CMD 0x0100
108 #define PP_EE_EWEN_CMD 0x00F0
109 #define PP_EE_EWDS_CMD 0x0000
110 #define PP_EE_ERASE_CMD 0x0300
112 #define PP_EE_DATA 0x0042
113 #define PP_EE_ADDR_W0 0x001C
114 #define PP_EE_ADDR_W1 0x001D
115 #define PP_EE_ADDR_W2 0x001E
117 #define EE_TIMEOUT 50000
118 __inline__ cyg_uint16 read_eeprom(cyg_addrword_t base, cyg_uint16 offset)
120 unsigned long timeout = EE_TIMEOUT;
121 if (get_reg(base, PP_SelfStat) & PP_SelfStat_EEPROM) {
123 diag_printf("EEPROM PP_SelfStat=0x%x\n", get_reg(base, PP_SelfStat));
126 diag_printf("Error: NO EEPROM present\n");
130 while ((timeout -- > 0) && (get_reg(base, PP_SelfStat) & PP_SelfStat_SIBSY))
133 diag_printf("read_eeprom() timeout\n");
136 timeout = EE_TIMEOUT;
137 put_reg(base, PP_ECR, (offset | PP_EE_READ_CMD));
138 while ((timeout -- > 0) && (get_reg(base, PP_SelfStat) & PP_SelfStat_SIBSY))
141 diag_printf("read_eeprom() timeout\n");
144 return get_reg(base, PP_EE_DATA);
148 * Write a word to an EEPROM location
149 * base: package page base (IO base)
150 * offset: the EEPROM word offset starting from 0. So for word 1, should pass in 1
151 * data: 16 bit data to be written into EEPRM
153 __inline__ void write_eeprom(cyg_addrword_t base, cyg_uint16 offset, cyg_uint16 data)
155 while (get_reg(base, PP_SelfStat) & PP_SelfStat_SIBSY)
157 put_reg(base, PP_ECR, PP_EE_EWEN_CMD);
158 while (get_reg(base, PP_SelfStat) & PP_SelfStat_SIBSY)
160 put_reg(base, PP_ECR, PP_EE_ERASE_CMD|offset);
161 while (get_reg(base, PP_SelfStat) & PP_SelfStat_SIBSY)
163 put_reg(base, PP_EE_DATA, data);
164 while (get_reg(base, PP_SelfStat) & PP_SelfStat_SIBSY)
166 put_reg(base, PP_ECR, (PP_EE_WRITE_CMD|offset));
167 while (get_reg(base, PP_SelfStat) & PP_SelfStat_SIBSY)
169 put_reg(base, PP_ECR, PP_EE_EWDS_CMD);
170 while (get_reg(base, PP_SelfStat) & PP_SelfStat_SIBSY)
174 #define CS8900A_RESET_BYPASS /* define it when reset is done early */
176 static __inline__ void copy_eeprom(cyg_addrword_t base)
180 for (i = 0; i < 6; i += 2) {
181 esa_word = read_eeprom(base, PP_EE_ADDR_W0 + (i/2));
182 put_reg(base, (PP_IA+i), esa_word);
183 // diag_printf("base=0x%x, copy_eeprom (0x%04x)\n", base, esa_word);
187 #undef CYGHWR_CL_CS8900A_PLF_RESET
188 #define CYGHWR_CL_CS8900A_PLF_RESET(base) copy_eeprom(base)
190 static cs8900a_priv_data_t cs8900a_eth0_priv_data = {
191 base : (cyg_addrword_t) BOARD_CS_LAN_BASE,
192 interrupt: CYGNUM_HAL_INTERRUPT_ETH,
193 #ifdef CYGSEM_DEVS_ETH_ARM_MXCBOARD_ETH0_SET_ESA
194 esa : CYGDAT_DEVS_ETH_ARM_MXCBOARD_ETH0_ESA,
195 hardwired_esa : true,
197 hardwired_esa : false,
199 #ifdef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
200 provide_esa : &_board_provide_eth0_esa,
206 ETH_DRV_SC(cs8900a_sc,
207 &cs8900a_eth0_priv_data, // Driver specific data
208 CYGDAT_DEVS_ETH_ARM_MXCBOARD_ETH0_NAME,
215 cs8900a_deliver, // "pseudoDSR" called from fast net thread
216 cs8900a_poll, // poll function, encapsulates ISR and DSR
219 NETDEVTAB_ENTRY(cs8900a_netdev,
220 "cs8900a_" CYGDAT_DEVS_ETH_ARM_MXCBOARD_ETH0_NAME,
224 #endif // CYGPKG_DEVS_ETH_ARM_MXCBOARD_ETH0
226 #endif // __WANT_DEVS