1 //==========================================================================
5 // NetSilion NET+ARM PHY chip configuration
7 //==========================================================================
8 //####ECOSGPLCOPYRIGHTBEGIN####
9 // -------------------------------------------
10 // This file is part of eCos, the Embedded Configurable Operating System.
11 // Copyright (C) 2005 eCosCentric LTD
13 // eCos is free software; you can redistribute it and/or modify it under
14 // the terms of the GNU General Public License as published by the Free
15 // Software Foundation; either version 2 or (at your option) any later version.
17 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
18 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
19 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
22 // You should have received a copy of the GNU General Public License along
23 // with eCos; if not, write to the Free Software Foundation, Inc.,
24 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
26 // As a special exception, if other files instantiate templates or use macros
27 // or inline functions from this file, or you compile this file and link it
28 // with other works to produce a work based on this file, this file does not
29 // by itself cause the resulting work to be covered by the GNU General Public
30 // License. However the source code for this file must still be made available
31 // in accordance with section (3) of the GNU General Public License.
33 // This exception does not invalidate any other reasons why a work based on
34 // this file might be covered by the GNU General Public License.
35 //==========================================================================
36 //#####DESCRIPTIONBEGIN####
38 // Author(s): Harald Brandl (harald.brandl@fh-joanneum.at)
39 // Contributors: Harald Brandl
41 // Purpose: PHY chip configuration
44 //####DESCRIPTIONEND####
46 //==========================================================================
49 #include <pkgconf/devs_eth_arm_netarm.h>
50 #include <cyg/hal/hal_diag.h>
51 #include <cyg/hal/hal_io.h>
54 #define PHYS(_i_) (0x800 | _i_)
56 #define SysReg (unsigned int*)0xffb00004 // System Status Register
58 /* Function: void mii_poll_busy (void)
61 * This routine is responsible for waiting for the current PHY
62 * operation to complete.
68 void mii_poll_busy(void)
70 /* check to see if PHY is busy with read or write */
75 /* Function: void mii_reset (void)
79 * This routine resets the PHY.
87 MIIAR = PHYS(0); // select command register
88 MIIWDR = 0x8000; // reset
92 /* Function: cyg_bool mii_negotiate (void)
95 * This routine is responsible for causing the external Ethernet PHY
96 * to begin the negotatiation process.
106 cyg_bool mii_negotiate(void)
108 int timeout = 100000;
126 if(0x24 == (MIIRDR & 0x24))
136 /* Function: void mii_set_speed (cyg_bool speed, cyg_bool duplex)
140 * This routine will set the speed and duplex of the external PHY.
154 void mii_set_speed(cyg_bool speed, cyg_bool duplex)
156 unsigned long int timeout = 1000000;
158 MIIAR = PHYS(0); // select command register
159 MIIWDR = (speed << 13) | (duplex << 8); // set speed and duplex
165 MIIAR = PHYS(1); // select status register
174 /* Function: cyg_bool mii_check_speed
178 * This routine will check the operating speed of the ethernet
189 cyg_bool mii_check_speed(void)
194 return (MIIRDR >> 14) & 1;
197 /* Function: void mii_check_duplex
201 * This routine will check the operating duplex of the ethernet
212 cyg_bool mii_check_duplex(void)
217 return (MIIRDR >> 9) & 1;