1 //==========================================================================
5 // National Semiconductor DP83816 ethernet chip
7 //==========================================================================
8 //####ECOSGPLCOPYRIGHTBEGIN####
9 // -------------------------------------------
10 // This file is part of eCos, the Embedded Configurable Operating System.
11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
12 // Copyright (C) 2003 Gary Thomas
13 // Copyright (C) 2004 eCosCentric Limited
15 // eCos is free software; you can redistribute it and/or modify it under
16 // the terms of the GNU General Public License as published by the Free
17 // Software Foundation; either version 2 or (at your option) any later version.
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21 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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25 // with eCos; if not, write to the Free Software Foundation, Inc.,
26 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
28 // As a special exception, if other files instantiate templates or use macros
29 // or inline functions from this file, or you compile this file and link it
30 // with other works to produce a work based on this file, this file does not
31 // by itself cause the resulting work to be covered by the GNU General Public
32 // License. However the source code for this file must still be made available
33 // in accordance with section (3) of the GNU General Public License.
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36 // this file might be covered by the GNU General Public License.
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39 // at http://sources.redhat.com/ecos/ecos-license/
40 // -------------------------------------------
41 //####ECOSGPLCOPYRIGHTEND####
42 //==========================================================================
43 //#####DESCRIPTIONBEGIN####
51 //####DESCRIPTIONEND####
53 //==========================================================================
55 #include <cyg/hal/hal_io.h>
56 #include <pkgconf/devs_eth_ns_dp83816.h>
58 // ------------------------------------------------------------------------
62 // 0 disables all debug output
63 // 1 for process debug output
64 // 2 for added data IO output: get_reg, put_reg
65 // 4 for packet allocation/free output
66 // 8 for only startup status, so we can tell we're installed OK
68 __externC int norecurse;
70 #define DEBUG_FUNCTION() do { if (!norecurse) { norecurse=1; diag_printf("%s\n", __FUNCTION__); norecurse=0;}} while (0)
71 #define DEBUG_LINE() do { diag_printf("%d\n", __LINE__); } while (0)
73 #define DEBUG_FUNCTION() do {} while(0)
74 #define DEBUG_LINE() do {} while(0)
77 // ------------------------------------------------------------------------
79 typedef struct dp83816_bd {
80 volatile struct dp83816_bd *next; // Next descriptor
81 volatile unsigned long stat; // Buffer status & flags
82 volatile unsigned char *buf; // Buffer memory
83 volatile unsigned long key; // Internal use only
86 // ------------------------------------------------------------------------
87 // Private driver structure
88 typedef struct dp83816_priv_data {
89 char *esa_key; // RedBoot 'key' for device ESA
90 unsigned char *enaddr;
91 int rxnum; // Number of Rx buffers
92 unsigned char *rxbuf; // Rx buffer space
93 dp83816_bd_t *rxd; // Rx descriptor pool
94 int txnum; // Number of Tx buffers
95 unsigned char *txbuf; // Tx buffer space
96 dp83816_bd_t *txd; // Tx descriptor pool
98 int interrupt; // Interrupt vector
99 #ifdef CYGINT_IO_ETH_INT_SUPPORT_REQUIRED
100 cyg_handle_t interrupt_handle;
101 cyg_interrupt interrupt_object;
103 dp83816_bd_t *rxnext; // Next Rx to interrupt
104 dp83816_bd_t *txfill; // Next Tx to fill
105 dp83816_bd_t *txint; // Next Tx to interrupt
106 int txbusy; // Number of busy Tx buffers
107 } dp83816_priv_data_t;
109 // ------------------------------------------------------------------------
110 // Macros for accessing DP registers
111 // These can be overridden by the platform header
112 // Note: the only accesses used must be 32 bit little endian.
115 # define DP_IN(_b_, _o_, _d_) HAL_READ_UINT32((cyg_addrword_t)(_b_)+(_o_), (_d_))
116 # define DP_OUT(_b_, _o_, _d_) HAL_WRITE_UINT32((cyg_addrword_t)(_b_)+(_o_), (_d_))
119 // ------------------------------------------------------------------------
120 // Macros allowing platform to customize some of the driver details
122 #ifndef CYGHWR_NS_DP83816_PLF_RESET
123 # define CYGHWR_NS_DP83816_PLF_RESET(_b_) do { } while (0)
126 #ifndef CYGHWR_NS_DP83816_PLF_INT_CLEAR
127 # define CYGHWR_NS_DP83816_PLF_INT_CLEAR(_dp_)
130 #ifndef CYGHWR_NS_DP83816_PLF_INIT
131 #define CYGHWR_NS_DP83816_PLF_INIT(dp) do { } while (0)
135 // ------------------------------------------------------------------------
136 // Some forward declarations
137 static void dp83816_poll(struct eth_drv_sc *sc);
139 // ------------------------------------------------------------------------
142 #define DP_CR 0x00 // Command register
143 #define _CR_RST 0x100 // Chip reset
144 #define _CR_RXR 0x020 // Rx reset
145 #define _CR_TXR 0x010 // Tx reset
146 #define _CR_RXD 0x008 // Rx disable
147 #define _CR_RXE 0x004 // Rx enable
148 #define _CR_TXD 0x002 // Tx disable
149 #define _CR_TXE 0x001 // Tx enable
150 #define DP_CFG 0x04 // Configuration register
151 #define _CFG_LNKSTS (1<<31) // Link status
152 #define _CFG_SPD100 (1<<30) // 100Mb
153 #define _CFG_FDUP (1<<29) // Full duplex
154 #define _CFG_POL (1<<28) // 10Mb polarity
155 #define _CFG_ANDONE (1<<27) // Auto-negotiation done
156 #define DP_MEAR 0x08 // EEPROM access
157 #define _MEAR_EESEL (1<<3) // EEPROM chip select
158 #define _MEAR_EECLK (1<<2) // EEPROM serial clock
159 #define _MEAR_EEDO (1<<1) // EEPROM data out
160 #define _MEAR_EEDI (1<<0) // EEPROM data in
161 #define DP_ISR 0x10 // Interrupt status
162 #define _ISR_TXRCMP (1<<25) // Tx reset complete
163 #define _ISR_RXRCMP (1<<24) // Rx reset complete
164 #define _ISR_DPERR (1<<23) // Detected parity error
165 #define _ISR_SSERR (1<<22) // Signalled system error
166 #define _ISR_RMABT (1<<21) // Received master abort
167 #define _ISR_RTABT (1<<20) // Received target abort
168 #define _ISR_RXSOVR (1<<16) // Rx status FIFO overrun
169 #define _ISR_HIBERR (1<<15) // High bits set (25-16)
170 #define _ISR_PHY (1<<14) // PHY interrupt
171 #define _ISR_PME (1<<13) // Power management event
172 #define _ISR_SWI (1<<12) // Software interrpt
173 #define _ISR_MIB (1<<11) // MII service
174 #define _ISR_TXURN (1<<10) // Tx underrun
175 #define _ISR_TXIDLE (1<<9) // Tx idle (end of list)
176 #define _ISR_TXERR (1<<8) // Tx packet error
177 #define _ISR_TXDESC (1<<7) // Tx descriptor with INTS
178 #define _ISR_TXOK (1<<6) // Last Tx descriptor done
179 #define _ISR_RXORN (1<<5) // Rx overrun
180 #define _ISR_RXIDLE (1<<4) // Rx idle (end of list)
181 #define _ISR_RXEARLY (1<<3) // Rx early threshold met
182 #define _ISR_RXERR (1<<2) // Rx packet error
183 #define _ISR_RXDESC (1<<1) // Rx descriptor with INTS
184 #define _ISR_RXOK (1<<0) // Last Rx descriptor done
185 #define DP_IMR 0x14 // Interrupt mask
186 #define DP_IER 0x18 // Interrupt enable
187 #define DP_IHR 0x1C // Interrupt hold
188 #define DP_TXDP 0x20 // Tx descriptor pointer
189 #define DP_TXCFG 0x24 // Tx configuration
190 #define _TXCFG_CSI (1<<31) // Ignore carrier sense
191 #define _TXCFG_HBI (1<<30) // Ignore heartbeat
192 #define _TXCFG_MLB (1<<29) // Loopback
193 #define _TXCFG_ATP (1<<28) // Automatic padding
194 #define _TXCFG_ECRTRY (1<<23) // Excessive collision enable
195 #define _TXCFG_MXDMA_SHIFT 20
196 #define _TXCFG_MXDMA_MASK 0x7
197 #define _TXCFG_MXDMA_512 (0x0<<20)
198 #define _TXCFG_MXDMA_4 (0x1<<20)
199 #define _TXCFG_MXDMA_8 (0x2<<20)
200 #define _TXCFG_MXDMA_16 (0x3<<20)
201 #define _TXCFG_MXDMA_32 (0x4<<20)
202 #define _TXCFG_MXDMA_64 (0x5<<20)
203 #define _TXCFG_MXDMA_128 (0x6<<20)
204 #define _TXCFG_MXDMA_256 (0x7<<20)
205 #define _TXCFG_FLTH_SHIFT 8
206 #define _TXCFG_FLTH_MASK 0x3F
207 #define _TXCFG_DRTH_SHIFT 0
208 #define _TXCFG_DRTH_MASK 0x3F
209 #define DP_RXDP 0x30 // Rx descriptor pointer
210 #define DP_RXCFG 0x34 // Rx configuration
211 #define _RXCFG_AEP (1<<31) // Accept error packets
212 #define _RXCFG_ARP (1<<30) // Accept runt packets
213 #define _RXCFG_ATX (1<<28) // Accept Tx packets (loopback)
214 #define _RXCFG_ALP (1<<27) // Accpet long packets (> 1518 bytes)
215 #define _RXCFG_MXDMA_SHIFT 20
216 #define _RXCFG_MXDMA_MASK 0x7
217 #define _RXCFG_MXDMA_512 (0x0<<20)
218 #define _RXCFG_MXDMA_4 (0x1<<20)
219 #define _RXCFG_MXDMA_8 (0x2<<20)
220 #define _RXCFG_MXDMA_16 (0x3<<20)
221 #define _RXCFG_MXDMA_32 (0x4<<20)
222 #define _RXCFG_MXDMA_64 (0x5<<20)
223 #define _RXCFG_MXDMA_128 (0x6<<20)
224 #define _RXCFG_MXDMA_256 (0x7<<20)
225 #define _RXCFG_FLTH_SHIFT 8
226 #define _RXCFG_FLTH_MASK 0x3F
227 #define _RXCFG_DRTH_SHIFT 0
228 #define _RXCFG_DRTH_MASK 0x3F
229 #define DP_RFCR 0x48 // Receive filter control
230 #define _RFCR_RFEN (1<<31) // Rx filter enable
231 #define _RFCR_AAB (1<<30) // Accept all broadcast
232 #define _RFCR_AAM (1<<29) // Accept all multicast
233 #define _RFCR_AAU (1<<28) // Accept all unicast
234 #define _RFCR_APM (1<<27) // Accept on perfect match
235 #define _RFCR_APAT (1<<26) // Accept on patern match
236 #define _RFCR_AARP (1<<22) // Accept ARP
237 #define _RFCR_MHEN (1<<21) // Multicast hash enable
238 #define _RFCR_UHEN (1<<20) // Unicast hash enable
239 #define _RFCR_ULM (1<<19) // U/L bit ignore
240 #define DP_RFDR 0x4C // Receive filter data register
242 // Buffer descriptor status/flags
243 #define BD_OWN (1<<31) // Owned by producer (Tx=driver, Rx=DP83816)
244 #define BD_MORE (1<<30) // More descriptors in this frame
245 #define BD_INTR (1<<29) // Interrupt when this descriptor processed
246 #define BD_CRC (1<<28) // Include CRC
247 #define BD_OK (1<<27) // Packet OK
249 #define BD_TXA (1<<26) // Tx abort
250 #define BD_TFU (1<<25) // Tx underrun
251 #define BD_CRS (1<<24) // Carrier sense lost
252 #define BD_TD (1<<23) // Transmission deferred
253 #define BD_ED (1<<22) // Excessive Tx deferrals
254 #define BD_OWC (1<<21) // Out of window collision
255 #define BD_EC (1<<20) // Excessive collisions
256 #define BD_CCNT_MASK 0x0F
257 #define BD_CCNT_SHIFT 16 // Collision count
259 #define BD_RXA (1<<26) // Rx abort
260 #define BD_RXO (1<<25) // Rx overrun
261 #define BD_DEST_MASK (3<<23)
262 #define BD_DEST_REJECT (0<<23) // Packet rejected
263 #define BD_DEST_UNICAST (1<<23) // Unicast packet
264 #define BD_DEST_MULTICAST (2<<23) // Multicast packet
265 #define BD_DEST_BROADCAST (3<<23) // Broadcast packet
266 #define BD_LONG (1<<22) // Too long packet received
267 #define BD_RUNT (1<<21) // Runt packet
268 #define BD_ISE (1<<20) // Illegal symbol
269 #define BD_CRCE (1<<19) // CRC error
270 #define BD_FAE (1<<18) // Frame alignment error
271 #define BD_LBP (1<<17) // Loopback frame
272 #define BD_COL (1<<16) // Collision during frame
274 #define BD_LENGTH_MASK 0x0FFF
276 #define IEEE_8023_MAX_FRAME 1518 // Largest possible ethernet frame
277 #define IEEE_8023_MIN_FRAME 64 // Smallest possible ethernet frame
279 #define _DP83816_BUFSIZE 1540 // Size of buffers