3 //==========================================================================
7 // Flash programming to support NAND flash on Freescale MXC platforms
9 //==========================================================================
10 //####ECOSGPLCOPYRIGHTBEGIN####
11 // -------------------------------------------
12 // This file is part of eCos, the Embedded Configurable Operating System.
13 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
15 // eCos is free software; you can redistribute it and/or modify it under
16 // the terms of the GNU General Public License as published by the Free
17 // Software Foundation; either version 2 or (at your option) any later version.
19 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
20 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
21 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
24 // You should have received a copy of the GNU General Public License along
25 // with eCos; if not, write to the Free Software Foundation, Inc.,
26 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
28 // As a special exception, if other files instantiate templates or use macros
29 // or inline functions from this file, or you compile this file and link it
30 // with other works to produce a work based on this file, this file does not
31 // by itself cause the resulting work to be covered by the GNU General Public
32 // License. However the source code for this file must still be made available
33 // in accordance with section (3) of the GNU General Public License.
35 // This exception does not invalidate any other reasons why a work based on
36 // this file might be covered by the GNU General Public License.
38 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
39 // at http://sources.redhat.com/ecos/ecos-license/
40 // -------------------------------------------
41 //####ECOSGPLCOPYRIGHTEND####
42 //==========================================================================
43 //#####DESCRIPTIONBEGIN####
45 // Author(s): Kevin Zhang <k.zhang@freescale.com>
46 // Contributors: Kevin Zhang <k.zhang@freescale.com>
51 //####DESCRIPTIONEND####
53 //==========================================================================
55 #include <pkgconf/devs_flash_onmxc.h>
56 #include "mxc_nand_specifics.h"
58 #define PG_2K_DATA_OP_MULTI_CYCLES() false
59 #define ADDR_INPUT_SIZE 8
61 #define NAND_MAIN_BUF0 (NFC_BASE + 0x000)
62 #define NAND_MAIN_BUF1 (NFC_BASE + 0x200)
63 #define NAND_MAIN_BUF2 (NFC_BASE + 0x400)
64 #define NAND_MAIN_BUF3 (NFC_BASE + 0x600)
65 #define NAND_MAIN_BUF4 (NFC_BASE + 0x800)
66 #define NAND_MAIN_BUF5 (NFC_BASE + 0xA00)
67 #define NAND_MAIN_BUF6 (NFC_BASE + 0xC00)
68 #define NAND_MAIN_BUF7 (NFC_BASE + 0xE00)
69 #define NAND_SPAR_BUF0 (NFC_BASE + 0x1000)
70 #define NAND_SPAR_BUF1 (NFC_BASE + 0x1040)
71 #define NAND_SPAR_BUF2 (NFC_BASE + 0x1080)
72 #define NAND_SPAR_BUF3 (NFC_BASE + 0x10C0)
73 #define NAND_SPAR_BUF4 (NFC_BASE + 0x1100)
74 #define NAND_SPAR_BUF5 (NFC_BASE + 0x1140)
75 #define NAND_SPAR_BUF6 (NFC_BASE + 0x1180)
76 #define NAND_SPAR_BUF7 (NFC_BASE + 0x11C0)
78 // The following defines are not used. Just for compilation purpose
79 #define ECC_STATUS_RESULT_REG 0xDEADFFFF
80 #define NFC_DATA_INPUT(buf_no, earea, en)
81 #define NFC_DATA_INPUT_2k(buf_no)
82 // dummy function as it is not needed for automatic operations
83 #define NFC_ADDR_INPUT(addr)
84 #define NFC_ARCH_INIT()
85 #define NUM_OF_CS_LINES 8
86 #define NFC_BUFSIZE 4096
88 enum nfc_internal_buf {
99 enum nfc_output_mode {
100 FDO_PAGE_SPARE = 0x0008,
101 FDO_SPARE_ONLY = 0x1008, // LSB has to be 0x08
102 FDO_FLASH_ID = 0x0010,
103 FDO_FLASH_STATUS = 0x0020,
106 #define wait_for_auto_prog_done() \
108 while ((nfc_reg_read(NFC_IPC_REG) & NFC_IPC_AUTO_DONE) == 0) { \
110 write_nfc_ip_reg((nfc_reg_read(NFC_IPC_REG) & ~NFC_IPC_AUTO_DONE), NFC_IPC_REG); \
113 // Polls the NANDFC to wait for an operation to complete
114 #define wait_op_done() \
116 while ((nfc_reg_read(NFC_IPC_REG) & NFC_IPC_INT) == 0) \
118 write_nfc_ip_reg(0, NFC_IPC_REG); \
122 #define nfc_reg_write(v, r) __nfc_reg_write(v, (void *)(r), #r, __FUNCTION__)
123 static inline void __nfc_reg_write(u32 val, void *addr,
124 const char *reg, const char *fn)
126 diag_printf1("%s: Writing %08x to %s[%04lx]\n", fn, val, reg,
127 (unsigned long)addr & 0x1fff);
131 #define nfc_reg_read(r) __nfc_reg_read((void *)(r), #r, __FUNCTION__)
132 static inline u32 __nfc_reg_read(void *addr,
133 const char *reg, const char *fn)
137 diag_printf1("%s: Read %08x from %s[%04lx]\n", fn, val, reg,
138 (unsigned long)addr & 0x1fff);
142 #define nfc_reg_read(r) readl(r)
143 #define nfc_reg_write(v, r) writel(v, r)
146 static void write_nfc_ip_reg(u32 val, u32 reg)
148 nfc_reg_write(NFC_IPC_CREQ, NFC_IPC_REG);
149 while((nfc_reg_read(NFC_IPC_REG) & NFC_IPC_CACK) == 0);
151 nfc_reg_write(val, reg);
152 nfc_reg_write((nfc_reg_read(NFC_IPC_REG) & ~NFC_IPC_CREQ), NFC_IPC_REG);
156 * NAND flash data output operation (reading data from NAND flash)
157 * @param buf_no internal ram buffer number that will contain data
158 * to be outputted from the NAND flash after operation done
159 * @param mode one of the mode defined in enum nfc_output_mode
160 * @param ecc_en 1 - ecc enabled; 0 - ecc disabled
162 static void NFC_DATA_OUTPUT(enum nfc_internal_buf buf_no, enum nfc_output_mode mode,
165 u32 v = nfc_reg_read(NFC_FLASH_CONFIG2_REG);
167 if ((v & NFC_FLASH_CONFIG2_ECC_EN) != 0 && ecc_en == 0) {
168 write_nfc_ip_reg(v & ~NFC_FLASH_CONFIG2_ECC_EN, NFC_FLASH_CONFIG2_REG);
170 if ((v & NFC_FLASH_CONFIG2_ECC_EN) == 0 && ecc_en != 0) {
171 write_nfc_ip_reg(v | NFC_FLASH_CONFIG2_ECC_EN, NFC_FLASH_CONFIG2_REG);
174 v = nfc_reg_read(NAND_CONFIGURATION1_REG);
176 if (mode == FDO_SPARE_ONLY) {
177 v = (v & ~0x71) | buf_no | NAND_CONFIGURATION1_SP_EN;
179 v = (v & ~0x71) | buf_no;
182 nfc_reg_write(v, NAND_CONFIGURATION1_REG);
184 nfc_reg_write(mode & 0xFF, NAND_LAUNCH_REG);
188 static void NFC_CMD_INPUT(u32 cmd)
190 nfc_reg_write(cmd & 0xFFFF, NAND_CMD_REG);
191 nfc_reg_write(NAND_LAUNCH_FCMD, NAND_LAUNCH_REG);
195 static void NFC_SET_NFC_ACTIVE_CS(u32 cs_line)
199 v = nfc_reg_read(NAND_CONFIGURATION1_REG) & (~0x7071);
200 v |= (cs_line << 12);
201 nfc_reg_write(v, NAND_CONFIGURATION1_REG);
204 static u16 NFC_STATUS_READ(void)
211 return nfc_reg_read(NAND_STATUS_SUM_REG);
213 /* Cannot rely on STATUS_SUM register due to errata */
214 for (i = 0; i < num_of_nand_chips; i++) {
215 NFC_SET_NFC_ACTIVE_CS(i);
217 nfc_reg_write(NAND_LAUNCH_AUTO_STAT, NAND_LAUNCH_REG);
218 status = (nfc_reg_read(NAND_CONFIGURATION1_REG) & 0x00FF0000) >> 16;
219 } while ((status & 0x40) == 0); // make sure I/O 6 == 1
220 /* Get Pass/Fail status */
221 status = (nfc_reg_read(NAND_CONFIGURATION1_REG) >> 16) & 0x1;
222 status_sum |= (status << i);
228 /* This function uses a global variable for the page size. It shouldn't be a big
229 * problem since we don't expect mixed page size nand flash parts on the same IC.
230 * Note for address 0, it will always be correct regardless the page size. So for
231 * ID read, it doesn't need to have the correct page size global variable first.
233 static void start_nfc_addr_ops(u32 ops, u32 pg_no, u16 pg_off, u32 is_erase, u32 cs_line, u32 num_of_chips)
235 u32 add0, add8, page_number;
236 int num_of_bits[] = {0, 0, 1, 0, 2, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 4};
238 if (ops == FLASH_Read_ID) {
240 nfc_reg_write(0x0, NAND_ADD0_REG + (4 * cs_line));
241 nfc_reg_write(NAND_LAUNCH_FADD, NAND_LAUNCH_REG);
246 if (num_of_chips > 1) {
247 page_number = (pg_no << num_of_bits[num_of_chips]) | (cs_line & (num_of_chips - 1));
255 // for both read and write
256 if (g_is_2k_page || g_is_4k_page) {
257 // the first two addr cycles are for column addr. Page number starts
258 // from the 3rd addr cycle.
259 add0 = pg_off | (page_number << 16);
260 add8 = page_number >> 16;
262 diag_printf("too bad, die\n");
264 // For 512B page, the first addr cycle is for column addr. Page number
265 // starts from the 2nd addr cycle.
266 add0 = (pg_off & 0xFF) | (page_number << 8);
267 add8 = page_number >> 24;
270 nfc_reg_write(add0, NAND_ADD0_REG);
271 nfc_reg_write(add8, NAND_ADD8_REG);
275 * Do a page read at random address
277 * @param pg_no page number offset from 0
278 * @param pg_off byte offset within the page
279 * @param ecc_force can force ecc to be off. Otherwise, by default it is on
280 * unless the page offset is non-zero
281 * @param cs_line indicates which NAND of interleaved NAND devices is used
283 * @return 0 if successful; non-zero otherwise
285 static int nfc_read_pg_random(u32 pg_no, u32 pg_off, u32 ecc_force, u32 cs_line, u32 num_of_chips)
287 u32 ecc = NFC_FLASH_CONFIG2_ECC_EN;
290 // clear the NAND_STATUS_SUM_REG register
291 nfc_reg_write(0, NAND_STATUS_SUM_REG);
293 // the 2nd condition is to test for unaligned page address -- ecc has to be off.
294 if (ecc_force == ECC_FORCE_OFF || pg_off != 0 ) {
298 // Take care of config1 for RBA and SP_EN
299 v = nfc_reg_read(NAND_CONFIGURATION1_REG) & (~0x71);
300 nfc_reg_write(v, NAND_CONFIGURATION1_REG);
303 v = nfc_reg_read(NFC_FLASH_CONFIG2_REG) & (~NFC_FLASH_CONFIG2_ECC_EN);
304 // setup config2 register for ECC enable or not
305 write_nfc_ip_reg(v | ecc, NFC_FLASH_CONFIG2_REG);
307 start_nfc_addr_ops(FLASH_Read_Mode1, pg_no, pg_off, 0, cs_line, num_of_chips);
309 if (g_is_2k_page || g_is_4k_page) {
310 // combine the two commands for 2k/4k page read
311 nfc_reg_write((FLASH_Read_Mode1_LG << 8) | FLASH_Read_Mode1, NAND_CMD_REG);
313 // just one command is enough for 512 page
314 nfc_reg_write(FLASH_Read_Mode1, NAND_CMD_REG);
318 nfc_reg_write(NAND_LAUNCH_AUTO_READ, NAND_LAUNCH_REG);
321 v = nfc_reg_read(NAND_STATUS_SUM_REG);
322 // test for CS0 ECC error from the STATUS_SUM register
323 if ((v & (0x0100 << cs_line)) != 0) {
325 nfc_reg_write((0x0100 << cs_line), NAND_STATUS_SUM_REG);
326 diag_printf("ECC error from NAND_STATUS_SUM_REG(0x%x) = 0x%x\n",
327 NAND_STATUS_SUM_REG, v);
328 diag_printf("NAND_ECC_STATUS_RESULT_REG(0x%x) = 0x%x\n", NAND_ECC_STATUS_RESULT_REG,
329 nfc_reg_read(NAND_ECC_STATUS_RESULT_REG));
336 * The NFC has to be preset before performing any operation
338 static void NFC_PRESET(u32 max_block_count)
340 // not needed. It is done in plf_hardware_init()
343 #endif // _MXC_NFC_V3_H_