1 #ifndef CYGONCE_ARM_S3C4510_SERIAL_H
2 #define CYGONCE_ARM_S3C4510_SERIAL_H
3 // ====================================================================
7 // Device I/O - Description of ARM S3C4510 serial hardware
9 // ====================================================================
10 //####ECOSGPLCOPYRIGHTBEGIN####
11 // -------------------------------------------
12 // This file is part of eCos, the Embedded Configurable Operating System.
13 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
15 // eCos is free software; you can redistribute it and/or modify it under
16 // the terms of the GNU General Public License as published by the Free
17 // Software Foundation; either version 2 or (at your option) any later version.
19 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
20 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
21 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
24 // You should have received a copy of the GNU General Public License along
25 // with eCos; if not, write to the Free Software Foundation, Inc.,
26 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
28 // As a special exception, if other files instantiate templates or use macros
29 // or inline functions from this file, or you compile this file and link it
30 // with other works to produce a work based on this file, this file does not
31 // by itself cause the resulting work to be covered by the GNU General Public
32 // License. However the source code for this file must still be made available
33 // in accordance with section (3) of the GNU General Public License.
35 // This exception does not invalidate any other reasons why a work based on
36 // this file might be covered by the GNU General Public License.
38 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
39 // at http://sources.redhat.com/ecos/ecos-license/
40 // -------------------------------------------
41 //####ECOSGPLCOPYRIGHTEND####
42 // ====================================================================
43 //#####DESCRIPTIONBEGIN####
45 // Author(s): Lars.Lindqvist@combitechsystems.com
46 // Contributors: jlarmour
48 // Purpose: Internal interfaces for serial I/O drivers
51 //####DESCRIPTIONEND####
53 // ====================================================================
55 #include <pkgconf/hal.h> // Value CYGNUM_HAL_ARM_S3C4510_CLOCK_SPEED needed
56 #include <cyg/infra/cyg_type.h> // base types
58 // Description of serial ports on ARM S3C4510
64 #define REG(n) _reg[n]
67 #define U_NOT_SUPP (0xFFFFFFFF) // Used to indicate unsupported parameter values
70 #define REG_ULCON REG(0) // Line control registers
71 #define REG_UCON REG(1) // Control registers
72 #define REG_USTAT REG(2) // Status registers
73 #define REG_UTXBUF REG(3) // Transmit buffer registers
74 #define REG_URXBUF REG(4) // Receive buffer registers
75 #define REG_UBRDIV REG(5) // Baud rate divisor registers
77 // Line Control Register Values
78 #define ULCON_WL5 (0x00000000 << 0) // Word length 5
79 #define ULCON_WL6 (0x00000001 << 0) // Word length 6
80 #define ULCON_WL7 (0x00000002 << 0) // Word length 7
81 #define ULCON_WL8 (0x00000003 << 0) // Word length 8
82 #define ULCON_STB1 (0x00000000 << 2) // One stop bit
83 #define ULCON_STB2 (0x00000001 << 2) // Two stop bits
84 #define ULCON_PMDOFF (0x00000000 << 3) // No parity
85 #define ULCON_PMDODD (0x00000004 << 3) // Odd parity
86 #define ULCON_PMDEVEN (0x00000005 << 3) // Even parity
87 #define ULCON_PMDFC1 (0x00000006 << 3) // Parity forced/checked as 1
88 #define ULCON_PMDFC0 (0x00000007 << 3) // Parity forced/checked as 0
89 #define ULCON_SCI (0x00000000 << 6) // Internal clock
90 #define ULCON_SCE (0x00000001 << 6) // External clock
91 #define ULCON_IROFF (0x00000000 << 7) // Normal mode
92 #define ULCON_IRON (0x00000001 << 7) // IR mode
94 // Control Register Values
95 #define UCON_RXMOFF (0x00000000 << 0) // Disable Rx mode
96 #define UCON_RXMINT (0x00000001 << 0) // Interrupt request Rx mode
97 #define UCON_RXMDMA0 (0x00000002 << 0) // GDMA channel 0 request Rx mode
98 #define UCON_RXMDMA1 (0x00000003 << 0) // GDMA channel 1 request Rx mode
99 #define UCON_RXSIOFF (0x00000000 << 2) // Rx status interrupt disabled
100 #define UCON_RXSION (0x00000001 << 2) // Rx status interrupt enabled
101 #define UCON_TXMOFF (0x00000000 << 3) // Disable Tx mode
102 #define UCON_TXMINT (0x00000001 << 3) // Interrupt request Tx mode
103 #define UCON_TXMDMA0 (0x00000002 << 3) // GDMA channel 0 request Tx mode
104 #define UCON_TXMDMA1 (0x00000003 << 3) // GDMA channel 1 request Tx mode
105 #define UCON_DSROFF (0x00000000 << 5) // Data set ready output off
106 #define UCON_DSRON (0x00000001 << 5) // Data set ready output on
107 #define UCON_SBKOFF (0x00000000 << 6) // No break sent
108 #define UCON_SBKON (0x00000001 << 6) // Break sent
109 #define UCON_LPBOFF (0x00000000 << 7) // Loop back mode off// Baud rate divisor registers
110 #define UCON_LPBON (0x00000001 << 7) // Loop back mode on^M
112 // Status Register Values
113 #define USTAT_OV (0x00000001 << 0) // Overrun error
114 #define USTAT_PE (0x00000001 << 1) // Parity error
115 #define USTAT_FE (0x00000001 << 2) // Frame error
117 #define USTAT_BKD (0x00000001 << 3) // Break detect
118 #define USTAT_DTR (0x00000001 << 4) // Data terminal ready
119 #define USTAT_RDR (0x00000001 << 5) // Receive data ready
120 #define USTAT_TBE (0x00000001 << 6) // Transmit buffer register empty
121 #define USTAT_TC (0x00000001 << 7) // Transmit complete
123 // Baud rate divisor registers
124 #define UBRDIV_50 ((((CYGNUM_HAL_ARM_S3C4510_CLOCK_SPEED/2/16/16/50)-1)<<4)|1)
125 #define UBRDIV_75 ((((CYGNUM_HAL_ARM_S3C4510_CLOCK_SPEED/2/16/16/75)-1)<<4)|1)
126 #define UBRDIV_110 ((((CYGNUM_HAL_ARM_S3C4510_CLOCK_SPEED/2/16/16/110)-1)<<4)|1)
127 #define UBRDIV_134_5 ((((CYGNUM_HAL_ARM_S3C4510_CLOCK_SPEED/2/16/8/269)-1)<<4)|1)
128 #define UBRDIV_150 ((((CYGNUM_HAL_ARM_S3C4510_CLOCK_SPEED/2/16/16/150)-1)<<4)|1)
129 #define UBRDIV_200 ((((CYGNUM_HAL_ARM_S3C4510_CLOCK_SPEED/2/16/16/200)-1)<<4)|1)
130 #define UBRDIV_300 ((((CYGNUM_HAL_ARM_S3C4510_CLOCK_SPEED/2/16/16/300)-1)<<4)|1)
131 #define UBRDIV_600 ((((CYGNUM_HAL_ARM_S3C4510_CLOCK_SPEED/2/1/16/600)-1)<<4)|0)
132 #define UBRDIV_1200 ((((CYGNUM_HAL_ARM_S3C4510_CLOCK_SPEED/2/1/16/1200)-1)<<4)|0)
133 #define UBRDIV_1800 ((((CYGNUM_HAL_ARM_S3C4510_CLOCK_SPEED/2/1/16/1800)-1)<<4)|0)
134 #define UBRDIV_2400 ((((CYGNUM_HAL_ARM_S3C4510_CLOCK_SPEED/2/1/16/2400)-1)<<4)|0)
135 #define UBRDIV_3600 ((((CYGNUM_HAL_ARM_S3C4510_CLOCK_SPEED/2/1/16/3600)-1)<<4)|0)
136 #define UBRDIV_4800 ((((CYGNUM_HAL_ARM_S3C4510_CLOCK_SPEED/2/1/16/4800)-1)<<4)|0)
137 #define UBRDIV_7200 ((((CYGNUM_HAL_ARM_S3C4510_CLOCK_SPEED/2/1/16/7200)-1)<<4)|0)
138 #define UBRDIV_9600 ((((CYGNUM_HAL_ARM_S3C4510_CLOCK_SPEED/2/1/16/9600)-1)<<4)|0)
139 #define UBRDIV_14400 ((((CYGNUM_HAL_ARM_S3C4510_CLOCK_SPEED/2/1/16/14400)-1)<<4)|0)
140 #define UBRDIV_19200 ((((CYGNUM_HAL_ARM_S3C4510_CLOCK_SPEED/2/1/16/19200)-1)<<4)|0)
141 #define UBRDIV_38400 ((((CYGNUM_HAL_ARM_S3C4510_CLOCK_SPEED/2/1/16/38400)-1)<<4)|0)
142 #define UBRDIV_57600 ((((CYGNUM_HAL_ARM_S3C4510_CLOCK_SPEED/2/1/16/57600)-1)<<4)|0)
143 #define UBRDIV_115200 ((((CYGNUM_HAL_ARM_S3C4510_CLOCK_SPEED/2/1/16/115200)-1)<<4)|0)
144 #define UBRDIV_230400 ((((CYGNUM_HAL_ARM_S3C4510_CLOCK_SPEED/2/1/16/230400)-1)<<4)|0)
146 // Arrays used for conversion of eCos serial driver
147 // configuration parameters to parameters for S3C4510
149 static cyg_uint32 select_word_length[] = {
150 ULCON_WL5, // 5 bits / word (char)
156 static cyg_uint32 select_stop_bits[] = {
157 ULCON_STB1, // 1 stop bit
158 U_NOT_SUPP, // 1.5 stop bit not supported
159 ULCON_STB2 // 2 stop bits
162 static cyg_uint32 select_parity[] = {
163 ULCON_PMDOFF, // No parity
164 ULCON_PMDEVEN, // Even parity
165 ULCON_PMDODD, // Odd parity
166 ULCON_PMDFC1, // Mark parity
167 ULCON_PMDFC0, // Space parity
170 static cyg_uint32 select_baud[] = {
174 UBRDIV_134_5, // 134.5
186 UBRDIV_14400, // 14400
187 UBRDIV_19200, // 19200
188 UBRDIV_38400, // 38400
189 UBRDIV_57600, // 57600
190 UBRDIV_115200, // 115200
191 UBRDIV_230400, // 230400
194 #endif // CYGONCE_ARM_S3C4510_SERIAL_H
196 // EOF s3c4510_serial.h