1 //==========================================================================
3 // io/serial/mips/idt79s334a/mipsidt_serial.h
5 // MIPS IDT79S334A Serial I/O definitions.
7 //==========================================================================
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40 //==========================================================================
41 //#####DESCRIPTIONBEGIN####
43 // Author(s): tmichals based on driver by dmoseley, based on POWERPC driver by jskov
44 // Contributors: gthomas, jskov, dmoseley, tmichals
47 // Purpose: MIPS IDT79s334a reference platform serial device driver definitions.
48 // Description: IDT MIPS serial device driver definitions.
49 //####DESCRIPTIONEND####
50 //==========================================================================
52 // Description of serial ports on IDT board
54 // Interrupt Enable Register
60 // Line Control Register
61 #define LCR_WL5 0x00 // Word length
65 #define LCR_SB1 0x00 // Number of stop bits
66 #define LCR_SB1_5 0x04 // 1.5 -> only valid with 5 bit words
68 #define LCR_PN 0x00 // Parity mode - none
69 #define LCR_PE 0x0C // Parity mode - even
70 #define LCR_PO 0x08 // Parity mode - odd
71 #define LCR_PM 0x28 // Forced "mark" parity
72 #define LCR_PS 0x38 // Forced "space" parity
73 #define LCR_DL 0x80 // Enable baud rate latch
75 // Line Status Register
79 // Modem Control Register
82 #define MCR_INT 0x08 // Enable interrupts
84 // Interrupt status register
86 #define ISR_Rx_Line_Status 0x06
87 #define ISR_Rx_Avail 0x04
88 #define ISR_Rx_Char_Timeout 0x0C
89 #define ISR_Tx_Empty 0x02
90 #define IRS_Modem_Status 0x00
92 // FIFO control register
93 #define FCR_ENABLE 0x01
94 #define FCR_CLEAR_RCVR 0x02
95 #define FCR_CLEAR_XMIT 0x04
98 ////////////////////////////////////////////////////////////
101 #define IDTMIPS_SER_16550_BASE_A 0xB8000803
102 #define IDTMIPS_SER_16550_BASE_B 0xB8000823
103 #define SER_16550_BASE IDTMIPS_SER_16550_BASE_A
104 #define INTR_COM0_REG 0xB8000554
105 #define INTR_COM1_REG 0xB8000564
107 //-----------------------------------------------------------------------------
108 // Define the serial registers. The IDT board is equipped with a 16550C
110 #define SER_16550_RBR 0x00 // receiver buffer register, read, dlab = 0
111 #define SER_16550_THR 0x00 // transmitter holding register, write, dlab = 0
112 #define SER_16550_DLL 0x00 // divisor latch (LS), read/write, dlab = 1
113 #define SER_16550_IER 0x04 // interrupt enable register, read/write, dlab = 0
114 #define SER_16550_DLM 0x04 // divisor latch (MS), read/write, dlab = 1
115 #define SER_16550_IIR 0x08 // interrupt identification reg, read, dlab = 0
116 #define SER_16550_FCR 0x08 // fifo control register, write, dlab = 0
117 #define SER_16550_AFR 0x08 // alternate function reg, read/write, dlab = 1
118 #define SER_16550_LCR 0x0c // line control register, read/write
119 #define SER_16550_MCR 0x10 // modem control register, read/write
120 #define SER_16550_LSR 0x14 // line status register, read
121 #define SER_16550_MSR 0x18 // modem status register, read
122 #define SER_16550_SCR 0x1c // scratch pad register
124 // The interrupt enable register bits.
125 #define SIO_IER_ERDAI 0x01 // enable received data available irq
126 #define SIO_IER_ETHREI 0x02 // enable THR empty interrupt
127 #define SIO_IER_ELSI 0x04 // enable receiver line status irq
128 #define SIO_IER_EMSI 0x08 // enable modem status interrupt
130 // The interrupt identification register bits.
131 #define SIO_IIR_IP 0x01 // 0 if interrupt pending
132 #define SIO_IIR_ID_MASK 0x0e // mask for interrupt ID bits
134 // The line status register bits.
135 #define SIO_LSR_DR 0x01 // data ready
136 #define SIO_LSR_OE 0x02 // overrun error
137 #define SIO_LSR_PE 0x04 // parity error
138 #define SIO_LSR_FE 0x08 // framing error
139 #define SIO_LSR_BI 0x10 // break interrupt
140 #define SIO_LSR_THRE 0x20 // transmitter holding register empty
141 #define SIO_LSR_TEMT 0x40 // transmitter register empty
142 #define SIO_LSR_ERR 0x80 // any error condition
144 // The modem status register bits.
145 #define SIO_MSR_DCTS 0x01 // delta clear to send
146 #define SIO_MSR_DDSR 0x02 // delta data set ready
147 #define SIO_MSR_TERI 0x04 // trailing edge ring indicator
148 #define SIO_MSR_DDCD 0x08 // delta data carrier detect
149 #define SIO_MSR_CTS 0x10 // clear to send
150 #define SIO_MSR_DSR 0x20 // data set ready
151 #define SIO_MSR_RI 0x40 // ring indicator
152 #define SIO_MSR_DCD 0x80 // data carrier detect
154 // The line control register bits.
155 #define SIO_LCR_WLS0 0x01 // word length select bit 0
156 #define SIO_LCR_WLS1 0x02 // word length select bit 1
157 #define SIO_LCR_STB 0x04 // number of stop bits
158 #define SIO_LCR_PEN 0x08 // parity enable
159 #define SIO_LCR_EPS 0x10 // even parity select
160 #define SIO_LCR_SP 0x20 // stick parity
161 #define SIO_LCR_SB 0x40 // set break
162 #define SIO_LCR_DLAB 0x80 // divisor latch access bit
164 // The FIFO control register
165 #define SIO_FCR_FCR0 0x01 // enable xmit and rcvr fifos
166 #define SIO_FCR_FCR1 0x02 // clear RCVR FIFO
167 #define SIO_FCR_FCR2 0x04 // clear XMIT FIFO
168 /////////////////////////////////////////
171 static unsigned char select_word_length[] = {
172 LCR_WL5, // 5 bits / word (char)
178 static unsigned char select_stop_bits[] = {
180 LCR_SB1, // 1 stop bit
181 LCR_SB1_5, // 1.5 stop bit
182 LCR_SB2 // 2 stop bits
185 static unsigned char select_parity[] = {
187 LCR_PE, // Even parity
188 LCR_PO, // Odd parity
189 LCR_PM, // Mark parity
190 LCR_PS, // Space parity
194 static unsigned int select_baud[] = {
219 // EOF mipsidt_serial.h