packages/devs/serial/mips/vrc437x/v2_0/src/vrc437x_serial.c

   1 //==========================================================================
   2 //
   3 //      io/serial/mips/vrc437x_serial.c
   4 //
   5 //      Mips VRC437X Serial I/O Interface Module (interrupt driven)
   6 //
   7 //==========================================================================
   8 //####ECOSGPLCOPYRIGHTBEGIN####
   9 // -------------------------------------------
  10 // This file is part of eCos, the Embedded Configurable Operating System.
  11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
  12 //
  13 // eCos is free software; you can redistribute it and/or modify it under
  14 // the terms of the GNU General Public License as published by the Free
  15 // Software Foundation; either version 2 or (at your option) any later version.
  16 //
  17 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
  18 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
  19 // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  20 // for more details.
  21 //
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  23 // with eCos; if not, write to the Free Software Foundation, Inc.,
  24 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  25 //
  26 // As a special exception, if other files instantiate templates or use macros
  27 // or inline functions from this file, or you compile this file and link it
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  30 // License. However the source code for this file must still be made available
  31 // in accordance with section (3) of the GNU General Public License.
  32 //
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  34 // this file might be covered by the GNU General Public License.
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  37 // at http://sources.redhat.com/ecos/ecos-license/
  38 // -------------------------------------------
  39 //####ECOSGPLCOPYRIGHTEND####
  40 //==========================================================================
  41 //#####DESCRIPTIONBEGIN####
  42 //
  43 // Author(s):    gthomas
  44 // Contributors: gthomas
  45 // Date:         1999-04-15
  46 // Purpose:      VRC437X Serial I/O module (interrupt driven version)
  47 // Description:
  48 //
  49 //####DESCRIPTIONEND####
  50 //
  51 //==========================================================================
  52
  53 #include <pkgconf/system.h>
  54 #include <pkgconf/io_serial.h>
  55 #include <pkgconf/io.h>
  56 #include <cyg/io/io.h>
  57 #include <cyg/hal/hal_intr.h>
  58 #include <cyg/io/devtab.h>
  59 #include <cyg/io/serial.h>
  60
  61 #ifdef CYGPKG_IO_SERIAL_MIPS_VRC437X
  62
  63 #include "vrc437x_serial.h"
  64
  65 #if defined(CYGPKG_HAL_MIPS_LSBFIRST)
  66 #define VRC437X_SCC_BASE 0xC1000000
  67 #elif defined(CYGPKG_HAL_MIPS_MSBFIRST)
  68 #define VRC437X_SCC_BASE 0xC1000003
  69 #else
  70 #error MIPS endianness not defined by configuration
  71 #endif
  72
  73 #define VRC437X_SCC_INT  CYGNUM_HAL_INTERRUPT_DUART
  74 #define SCC_CHANNEL_A             4
  75 #define SCC_CHANNEL_B             0
  76
  77 extern void diag_printf(const char *fmt, ...);
  78
  79 typedef struct vrc437x_serial_info {
  80     CYG_ADDRWORD   base;
  81     unsigned char  regs[16];   // Known register state (since hardware is write-only!)
  82 } vrc437x_serial_info;
  83
  84 static bool vrc437x_serial_init(struct cyg_devtab_entry *tab);
  85 static bool vrc437x_serial_putc(serial_channel *chan, unsigned char c);
  86 static Cyg_ErrNo vrc437x_serial_lookup(struct cyg_devtab_entry **tab,
  87                                        struct cyg_devtab_entry *sub_tab,
  88                                        const char *name);
  89 static unsigned char vrc437x_serial_getc(serial_channel *chan);
  90 static Cyg_ErrNo vrc437x_serial_set_config(serial_channel *chan, cyg_uint32 key,
  91                                            const void *xbuf, cyg_uint32 *len);
  92 static void vrc437x_serial_start_xmit(serial_channel *chan);
  93 static void vrc437x_serial_stop_xmit(serial_channel *chan);
  94
  95 static cyg_uint32 vrc437x_serial_ISR(cyg_vector_t vector, cyg_addrword_t data);
  96 static void       vrc437x_serial_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data);
  97
  98 static SERIAL_FUNS(vrc437x_serial_funs,
  99                    vrc437x_serial_putc,
 100                    vrc437x_serial_getc,
 101                    vrc437x_serial_set_config,
 102                    vrc437x_serial_start_xmit,
 103                    vrc437x_serial_stop_xmit
 104     );
 105
 106 #ifdef CYGPKG_IO_SERIAL_MIPS_VRC437X_SERIAL0
 107 static vrc437x_serial_info vrc437x_serial_info0 = {VRC437X_SCC_BASE+SCC_CHANNEL_A};
 108 #if CYGNUM_IO_SERIAL_MIPS_VRC437X_SERIAL0_BUFSIZE > 0
 109 static unsigned char vrc437x_serial_out_buf0[CYGNUM_IO_SERIAL_MIPS_VRC437X_SERIAL0_BUFSIZE];
 110 static unsigned char vrc437x_serial_in_buf0[CYGNUM_IO_SERIAL_MIPS_VRC437X_SERIAL0_BUFSIZE];
 111
 112 static SERIAL_CHANNEL_USING_INTERRUPTS(vrc437x_serial_channel0,
 113                                        vrc437x_serial_funs,
 114                                        vrc437x_serial_info0,
 115                                        CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_MIPS_VRC437X_SERIAL0_BAUD),
 116                                        CYG_SERIAL_STOP_DEFAULT,
 117                                        CYG_SERIAL_PARITY_DEFAULT,
 118                                        CYG_SERIAL_WORD_LENGTH_DEFAULT,
 119                                        CYG_SERIAL_FLAGS_DEFAULT,
 120                                        &vrc437x_serial_out_buf0[0], sizeof(vrc437x_serial_out_buf0),
 121                                        &vrc437x_serial_in_buf0[0], sizeof(vrc437x_serial_in_buf0)
 122     );
 123 #else
 124 static SERIAL_CHANNEL(vrc437x_serial_channel0,
 125                       vrc437x_serial_funs,
 126                       vrc437x_serial_info0,
 127                       CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_MIPS_VRC437X_SERIAL0_BAUD),
 128                       CYG_SERIAL_STOP_DEFAULT,
 129                       CYG_SERIAL_PARITY_DEFAULT,
 130                       CYG_SERIAL_WORD_LENGTH_DEFAULT,
 131                       CYG_SERIAL_FLAGS_DEFAULT
 132     );
 133 #endif
 134
 135 DEVTAB_ENTRY(vrc437x_serial_io0,
 136              CYGDAT_IO_SERIAL_MIPS_VRC437X_SERIAL0_NAME,
 137              0,                     // Does not depend on a lower level interface
 138              &cyg_io_serial_devio,
 139              vrc437x_serial_init,
 140              vrc437x_serial_lookup,     // Serial driver may need initializing
 141              &vrc437x_serial_channel0
 142     );
 143 #endif //  CYGPKG_IO_SERIAL_MIPS_VRC437X_SERIAL0
 144
 145 #ifdef CYGPKG_IO_SERIAL_MIPS_VRC437X_SERIAL1
 146 static vrc437x_serial_info vrc437x_serial_info1 = {VRC437X_SCC_BASE+SCC_CHANNEL_B};
 147 #if CYGNUM_IO_SERIAL_MIPS_VRC437X_SERIAL1_BUFSIZE > 0
 148 static unsigned char vrc437x_serial_out_buf1[CYGNUM_IO_SERIAL_MIPS_VRC437X_SERIAL1_BUFSIZE];
 149 static unsigned char vrc437x_serial_in_buf1[CYGNUM_IO_SERIAL_MIPS_VRC437X_SERIAL1_BUFSIZE];
 150
 151 static SERIAL_CHANNEL_USING_INTERRUPTS(vrc437x_serial_channel1,
 152                                        vrc437x_serial_funs,
 153                                        vrc437x_serial_info1,
 154                                        CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_MIPS_VRC437X_SERIAL1_BAUD),
 155                                        CYG_SERIAL_STOP_DEFAULT,
 156                                        CYG_SERIAL_PARITY_DEFAULT,
 157                                        CYG_SERIAL_WORD_LENGTH_DEFAULT,
 158                                        CYG_SERIAL_FLAGS_DEFAULT,
 159                                        &vrc437x_serial_out_buf1[0], sizeof(vrc437x_serial_out_buf1),
 160                                        &vrc437x_serial_in_buf1[0], sizeof(vrc437x_serial_in_buf1)
 161     );
 162 #else
 163 static SERIAL_CHANNEL(vrc437x_serial_channel1,
 164                       vrc437x_serial_funs,
 165                       vrc437x_serial_info1,
 166                       CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_MIPS_VRC437X_SERIAL1_BAUD),
 167                       CYG_SERIAL_STOP_DEFAULT,
 168                       CYG_SERIAL_PARITY_DEFAULT,
 169                       CYG_SERIAL_WORD_LENGTH_DEFAULT,
 170                       CYG_SERIAL_FLAGS_DEFAULT
 171     );
 172 #endif
 173
 174 DEVTAB_ENTRY(vrc437x_serial_io1,
 175              CYGDAT_IO_SERIAL_MIPS_VRC437X_SERIAL1_NAME,
 176              0,                     // Does not depend on a lower level interface
 177              &cyg_io_serial_devio,
 178              vrc437x_serial_init,
 179              vrc437x_serial_lookup,     // Serial driver may need initializing
 180              &vrc437x_serial_channel1
 181     );
 182 #endif //  CYGPKG_IO_SERIAL_MIPS_VRC437X_SERIAL1
 183
 184 static cyg_interrupt  vrc437x_serial_interrupt;
 185 static cyg_handle_t   vrc437x_serial_interrupt_handle;
 186
 187 // Table which maps hardware channels (A,B) to software ones
 188 struct serial_channel *vrc437x_chans[] = {
 189 #ifdef CYGPKG_IO_SERIAL_MIPS_VRC437X_SERIAL0    // Hardware channel A
 190     &vrc437x_serial_channel0,
 191 #else
 192     0,
 193 #endif
 194 #ifdef CYGPKG_IO_SERIAL_MIPS_VRC437X_SERIAL1    // Hardware channel B
 195     &vrc437x_serial_channel1,
 196 #else
 197     0,
 198 #endif
 199 };
 200
 201 // Support functions which access the serial device.  Note that this chip requires
 202 // a substantial delay after each access.
 203
 204 #define SCC_DELAY 100
 205 inline static void
 206 scc_delay(void)
 207 {
 208     int i;
 209     for (i = 0;  i < SCC_DELAY;  i++) ;
 210 }
 211
 212 inline static void
 213 scc_write_reg(volatile unsigned char *reg, unsigned char val)
 214 {
 215     scc_delay();
 216     *reg = val;
 217 }
 218
 219 inline static unsigned char
 220 scc_read_reg(volatile unsigned char *reg)
 221 {
 222     unsigned char val;
 223     scc_delay();
 224     val = *reg;
 225     return (val);
 226 }
 227
 228 inline static unsigned char
 229 scc_read_ctl(volatile struct serial_port *port, int reg)
 230 {
 231     if (reg != 0) {
 232         scc_write_reg(&port->scc_ctl, reg);
 233     }
 234     return (scc_read_reg(&port->scc_ctl));
 235 }
 236
 237 inline static void
 238 scc_write_ctl(volatile struct serial_port *port, int reg, unsigned char val)
 239 {
 240     if (reg != 0) {
 241         scc_write_reg(&port->scc_ctl, reg);
 242     }
 243     scc_write_reg(&port->scc_ctl, val);
 244 }
 245
 246 inline static unsigned char
 247 scc_read_dat(volatile struct serial_port *port)
 248 {
 249     return (scc_read_reg(&port->scc_dat));
 250 }
 251
 252 inline static void
 253 scc_write_dat(volatile struct serial_port *port, unsigned char val)
 254 {
 255     scc_write_reg(&port->scc_dat, val);
 256 }
 257
 258 // Internal function to actually configure the hardware to desired baud rate, etc.
 259 static bool
 260 vrc437x_serial_config_port(serial_channel *chan, cyg_serial_info_t *new_config, bool init)
 261 {
 262     vrc437x_serial_info *vrc437x_chan = (vrc437x_serial_info *)chan->dev_priv;
 263     volatile struct serial_port *port = (volatile struct serial_port *)vrc437x_chan->base;
 264     cyg_int32 baud_rate = select_baud[new_config->baud];
 265     cyg_int32 baud_divisor;
 266     unsigned char *regs = &vrc437x_chan->regs[0];
 267     if (baud_rate == 0) return false;
 268     // Compute state of registers.  The register/control state needs to be kept in
 269     // the shadow variable 'regs' because the hardware registers can only be written,
 270     // not read (in general).
 271     if (init) {
 272         // Insert appropriate resets?
 273         if (chan->out_cbuf.len != 0) {
 274             regs[R1] = WR1_IntAllRx;
 275             regs[R9] = WR9_MIE | WR9_NoVector;
 276         } else {
 277             regs[R1] = 0;
 278             regs[R9] = 0;
 279         }
 280         // Clocks are from the baud rate generator
 281         regs[R11] = WR11_TRxCBR | WR11_TRxCOI | WR11_TxCBR | WR11_RxCBR;
 282         regs[R14] = WR14_BRenable | WR14_BRSRC;
 283         regs[R10] = 0;    // Unused in this [async] mode
 284         regs[R15] = 0;
 285     }
 286     regs[R3] = WR3_RxEnable | select_word_length_WR3[new_config->word_length - CYGNUM_SERIAL_WORD_LENGTH_5];
 287     regs[R4] = WR4_X16CLK | select_stop_bits[new_config->stop] | select_parity[new_config->parity];
 288     regs[R5] = WR5_TxEnable  | select_word_length_WR5[new_config->word_length - CYGNUM_SERIAL_WORD_LENGTH_5];
 289     baud_divisor = BRTC(baud_rate);
 290     regs[R12] = baud_divisor & 0xFF;
 291     regs[R13] = baud_divisor >> 8;
 292     // Now load the registers
 293     scc_write_ctl(port, R4, regs[R4]);
 294     scc_write_ctl(port, R10, regs[R10]);
 295     scc_write_ctl(port, R3, regs[R3] & ~WR3_RxEnable);
 296     scc_write_ctl(port, R5, regs[R5] & ~WR5_TxEnable);
 297     scc_write_ctl(port, R1, regs[R1]);
 298     scc_write_ctl(port, R9, regs[R9]);
 299     scc_write_ctl(port, R11, regs[R11]);
 300     scc_write_ctl(port, R12, regs[R12]);
 301     scc_write_ctl(port, R13, regs[R13]);
 302     scc_write_ctl(port, R14, regs[R14]);
 303     scc_write_ctl(port, R15, regs[R15]);
 304     scc_write_ctl(port, R3, regs[R3]);
 305     scc_write_ctl(port, R5, regs[R5]);
 306     // Update configuration
 307     if (new_config != &chan->config) {
 308         chan->config = *new_config;
 309     }
 310     return true;
 311 }
 312
 313 // Function to initialize the device.  Called at bootstrap time.
 314 static bool
 315 vrc437x_serial_init(struct cyg_devtab_entry *tab)
 316 {
 317     serial_channel *chan = (serial_channel *)tab->priv;
 318     vrc437x_serial_info *vrc437x_chan = (vrc437x_serial_info *)chan->dev_priv;
 319     static bool init = false;
 320 #ifdef CYGDBG_IO_INIT
 321     diag_printf("VRC437X SERIAL init '%s' - dev: %x\n", tab->name, vrc437x_chan->base);
 322 #endif
 323     (chan->callbacks->serial_init)(chan);  // Really only required for interrupt driven devices
 324     if (!init && chan->out_cbuf.len != 0) {
 325         init = true;
 326 // Note that the hardware is rather broken.  The interrupt status needs to
 327 // be read using only channel A
 328         cyg_drv_interrupt_create(VRC437X_SCC_INT,
 329                                  99,
 330                                  (cyg_addrword_t)VRC437X_SCC_BASE+SCC_CHANNEL_A,
 331                                  vrc437x_serial_ISR,
 332                                  vrc437x_serial_DSR,
 333                                  &vrc437x_serial_interrupt_handle,
 334                                  &vrc437x_serial_interrupt);
 335         cyg_drv_interrupt_attach(vrc437x_serial_interrupt_handle);
 336         cyg_drv_interrupt_unmask(VRC437X_SCC_INT);
 337     }
 338     vrc437x_serial_config_port(chan, &chan->config, true);
 339     return true;
 340 }
 341
 342 // This routine is called when the device is "looked" up (i.e. attached)
 343 static Cyg_ErrNo
 344 vrc437x_serial_lookup(struct cyg_devtab_entry **tab,
 345                   struct cyg_devtab_entry *sub_tab,
 346                   const char *name)
 347 {
 348     serial_channel *chan = (serial_channel *)(*tab)->priv;
 349     (chan->callbacks->serial_init)(chan);  // Really only required for interrupt driven devices
 350     return ENOERR;
 351 }
 352
 353 // Send a character to the device output buffer.
 354 // Return 'true' if character is sent to device
 355 static bool
 356 vrc437x_serial_putc(serial_channel *chan, unsigned char c)
 357 {
 358     vrc437x_serial_info *vrc437x_chan = (vrc437x_serial_info *)chan->dev_priv;
 359     volatile struct serial_port *port = (volatile struct serial_port *)vrc437x_chan->base;
 360     if (scc_read_ctl(port, R0) & RR0_TxEmpty) {
 361 // Transmit buffer is empty
 362         scc_write_dat(port, c);
 363         return true;
 364     } else {
 365 // No space
 366         return false;
 367     }
 368 }
 369
 370 // Fetch a character from the device input buffer, waiting if necessary
 371 static unsigned char
 372 vrc437x_serial_getc(serial_channel *chan)
 373 {
 374     unsigned char c;
 375     vrc437x_serial_info *vrc437x_chan = (vrc437x_serial_info *)chan->dev_priv;
 376     volatile struct serial_port *port = (volatile struct serial_port *)vrc437x_chan->base;
 377     while ((scc_read_ctl(port, R0) & RR0_RxAvail) == 0) ;   // Wait for char
 378     c = scc_read_dat(port);
 379     return c;
 380 }
 381
 382 // Set up the device characteristics; baud rate, etc.
 383 static Cyg_ErrNo
 384 vrc437x_serial_set_config(serial_channel *chan, cyg_uint32 key,
 385                           const void *xbuf, cyg_uint32 *len)
 386 {
 387     switch (key) {
 388     case CYG_IO_SET_CONFIG_SERIAL_INFO:
 389       {
 390         cyg_serial_info_t *config = (cyg_serial_info_t *)xbuf;
 391         if ( *len < sizeof(cyg_serial_info_t) ) {
 392             return -EINVAL;
 393         }
 394         *len = sizeof(cyg_serial_info_t);
 395         if ( true != vrc437x_serial_config_port(chan, config, false) )
 396             return -EINVAL;
 397       }
 398       break;
 399     default:
 400         return -EINVAL;
 401     }
 402     return ENOERR;
 403 }
 404
 405 // Enable the transmitter on the device
 406 static void
 407 vrc437x_serial_start_xmit(serial_channel *chan)
 408 {
 409     vrc437x_serial_info *vrc437x_chan = (vrc437x_serial_info *)chan->dev_priv;
 410     volatile struct serial_port *port = (volatile struct serial_port *)vrc437x_chan->base;
 411     if ((vrc437x_chan->regs[R1] & WR1_TxIntEnab) == 0) {
 412         CYG_INTERRUPT_STATE old;
 413         HAL_DISABLE_INTERRUPTS(old);
 414         vrc437x_chan->regs[R1] |= WR1_TxIntEnab;  // Enable Tx interrupt
 415         scc_write_ctl(port, R1, vrc437x_chan->regs[R1]);
 416         (chan->callbacks->xmt_char)(chan);  // Send first character to start xmitter
 417         HAL_RESTORE_INTERRUPTS(old);
 418     }
 419 }
 420
 421 // Disable the transmitter on the device
 422 static void
 423 vrc437x_serial_stop_xmit(serial_channel *chan)
 424 {
 425     vrc437x_serial_info *vrc437x_chan = (vrc437x_serial_info *)chan->dev_priv;
 426     volatile struct serial_port *port = (volatile struct serial_port *)vrc437x_chan->base;
 427     if ((vrc437x_chan->regs[R1] & WR1_TxIntEnab) != 0) {
 428         CYG_INTERRUPT_STATE old;
 429         HAL_DISABLE_INTERRUPTS(old);
 430         vrc437x_chan->regs[R1] &= ~WR1_TxIntEnab;  // Disable Tx interrupt
 431         scc_write_ctl(port, R1, vrc437x_chan->regs[R1]);
 432         HAL_RESTORE_INTERRUPTS(old);
 433     }
 434 }
 435
 436 // Serial I/O - low level interrupt handler (ISR)
 437 static cyg_uint32
 438 vrc437x_serial_ISR(cyg_vector_t vector, cyg_addrword_t data)
 439 {
 440     cyg_drv_interrupt_mask(VRC437X_SCC_INT);
 441     cyg_drv_interrupt_acknowledge(VRC437X_SCC_INT);
 442     return CYG_ISR_CALL_DSR;  // Cause DSR to be run
 443 }
 444
 445 inline static void
 446 vrc437x_int(serial_channel *chan, unsigned char stat)
 447 {
 448     vrc437x_serial_info *vrc437x_chan = (vrc437x_serial_info *)chan->dev_priv;
 449     volatile struct serial_port *port = (volatile struct serial_port *)vrc437x_chan->base;
 450     // Note: 'stat' value is interrupt status register, shifted into "B" position
 451     if (stat & RR3_BRxIP) {
 452         // Receive interrupt
 453         unsigned char c;
 454         c = scc_read_dat(port);
 455         (chan->callbacks->rcv_char)(chan, c);
 456     }
 457     if (stat & RR3_BTxIP) {
 458         // Transmit interrupt
 459         (chan->callbacks->xmt_char)(chan);
 460     }
 461     if (stat & RR3_BExt) {
 462         // Status interrupt (parity error, framing error, etc)
 463     }
 464 }
 465
 466 // Serial I/O - high level interrupt handler (DSR)
 467 // Note: This device presents a single interrupt for both channels.  Thus the
 468 // interrupt handler has to query the device and decide which channel needs service.
 469 // Additionally, more than one interrupt condition may be present so this needs to
 470 // be done in a loop until all interrupt requests have been handled.
 471 // Also note that the hardware is rather broken.  The interrupt status needs to
 472 // be read using only channel A (pointed to by 'data')
 473 static void
 474 vrc437x_serial_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data)
 475 {
 476     serial_channel *chan;
 477     volatile struct serial_port *port = (volatile struct serial_port *)data;
 478     unsigned char stat;
 479     while (true) {
 480         stat = scc_read_ctl(port, R3);
 481         if (stat & (RR3_AExt | RR3_ATxIP | RR3_ARxIP)) {
 482             chan = vrc437x_chans[0];  // Hardware channel A
 483             vrc437x_int(chan, stat>>3);  // Handle interrupt
 484         } else if (stat & (RR3_BExt | RR3_BTxIP | RR3_BRxIP)) {
 485             chan = vrc437x_chans[1];  // Hardware channel B
 486             vrc437x_int(chan, stat);  // Handle interrupt
 487         } else {
 488             // No more interrupts, all done
 489             break;
 490         }
 491     }
 492     cyg_drv_interrupt_unmask(VRC437X_SCC_INT);
 493 }
 494 #endif