1 //==========================================================================
3 // io/serial/powerpc/cogent_serial.h
5 // PowerPC Cogent Serial I/O definitions.
7 //==========================================================================
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40 //==========================================================================
41 //#####DESCRIPTIONBEGIN####
43 // Author(s): jskov, based on ARM driver by gthomas
44 // Contributors:gthomas, jskov
46 // Purpose: Cogent Serial definitions
47 //####DESCRIPTIONEND####
48 //==========================================================================
50 // Description of serial ports on Cogent board
52 // Interrupt Enable Register
58 // Line Control Register
59 #define LCR_WL5 0x00 // Word length
63 #define LCR_SB1 0x00 // Number of stop bits
64 #define LCR_SB1_5 0x04 // 1.5 -> only valid with 5 bit words
66 #define LCR_PN 0x00 // Parity mode - none
67 #define LCR_PE 0x0C // Parity mode - even
68 #define LCR_PO 0x08 // Parity mode - odd
69 #define LCR_PM 0x28 // Forced "mark" parity
70 #define LCR_PS 0x38 // Forced "space" parity
71 #define LCR_DL 0x80 // Enable baud rate latch
73 // Line Status Register
77 // Modem Control Register
80 #define MCR_INT 0x08 // Enable interrupts
82 // Interrupt status register
86 // FIFO control register
87 #define FCR_ENABLE 0x01
88 #define FCR_CLEAR_RCVR 0x02
89 #define FCR_CLEAR_XMIT 0x04
92 ////////////////////////////////////////////////////////////
95 //-----------------------------------------------------------------------------
96 // There are two serial ports.
97 #define CMA_SER_16550_BASE_A 0xe900047 // port A
98 #define CMA_SER_16550_BASE_B 0xe900007 // port B
99 #define SER_16550_BASE CMA_SER_16550_BASE_B
101 //-----------------------------------------------------------------------------
102 // Define the serial registers. The Cogent board is equipped with a 16552
104 #define SER_16550_RBR 0x00 // receiver buffer register, read, dlab = 0
105 #define SER_16550_THR 0x00 // transmitter holding register, write, dlab = 0
106 #define SER_16550_DLL 0x00 // divisor latch (LS), read/write, dlab = 1
107 #define SER_16550_IER 0x08 // interrupt enable register, read/write, dlab = 0
108 #define SER_16550_DLM 0x08 // divisor latch (MS), read/write, dlab = 1
109 #define SER_16550_IIR 0x10 // interrupt identification reg, read, dlab = 0
110 #define SER_16550_FCR 0x10 // fifo control register, write, dlab = 0
111 #define SER_16550_AFR 0x10 // alternate function reg, read/write, dlab = 1
112 #define SER_16550_LCR 0x18 // line control register, read/write
113 #define SER_16550_MCR 0x20 // modem control register, read/write
114 #define SER_16550_LSR 0x28 // line status register, read
115 #define SER_16550_MSR 0x30 // modem status register, read
116 #define SER_16550_SCR 0x38 // scratch pad register
118 // The interrupt enable register bits.
119 #define SIO_IER_ERDAI 0x01 // enable received data available irq
120 #define SIO_IER_ETHREI 0x02 // enable THR empty interrupt
121 #define SIO_IER_ELSI 0x04 // enable receiver line status irq
122 #define SIO_IER_EMSI 0x08 // enable modem status interrupt
124 // The interrupt identification register bits.
125 #define SIO_IIR_IP 0x01 // 0 if interrupt pending
126 #define SIO_IIR_ID_MASK 0x0e // mask for interrupt ID bits
128 // The line status register bits.
129 #define SIO_LSR_DR 0x01 // data ready
130 #define SIO_LSR_OE 0x02 // overrun error
131 #define SIO_LSR_PE 0x04 // parity error
132 #define SIO_LSR_FE 0x08 // framing error
133 #define SIO_LSR_BI 0x10 // break interrupt
134 #define SIO_LSR_THRE 0x20 // transmitter holding register empty
135 #define SIO_LSR_TEMT 0x40 // transmitter register empty
136 #define SIO_LSR_ERR 0x80 // any error condition
138 // The modem status register bits.
139 #define SIO_MSR_DCTS 0x01 // delta clear to send
140 #define SIO_MSR_DDSR 0x02 // delta data set ready
141 #define SIO_MSR_TERI 0x04 // trailing edge ring indicator
142 #define SIO_MSR_DDCD 0x08 // delta data carrier detect
143 #define SIO_MSR_CTS 0x10 // clear to send
144 #define SIO_MSR_DSR 0x20 // data set ready
145 #define SIO_MSR_RI 0x40 // ring indicator
146 #define SIO_MSR_DCD 0x80 // data carrier detect
148 // The line control register bits.
149 #define SIO_LCR_WLS0 0x01 // word length select bit 0
150 #define SIO_LCR_WLS1 0x02 // word length select bit 1
151 #define SIO_LCR_STB 0x04 // number of stop bits
152 #define SIO_LCR_PEN 0x08 // parity enable
153 #define SIO_LCR_EPS 0x10 // even parity select
154 #define SIO_LCR_SP 0x20 // stick parity
155 #define SIO_LCR_SB 0x40 // set break
156 #define SIO_LCR_DLAB 0x80 // divisor latch access bit
158 // The FIFO control register
159 #define SIO_FCR_FCR0 0x01 // enable xmit and rcvr fifos
160 #define SIO_FCR_FCR1 0x02 // clear RCVR FIFO
161 #define SIO_FCR_FCR2 0x04 // clear XMIT FIFO
162 /////////////////////////////////////////
165 static unsigned char select_word_length[] = {
166 LCR_WL5, // 5 bits / word (char)
172 static unsigned char select_stop_bits[] = {
174 LCR_SB1, // 1 stop bit
175 LCR_SB1_5, // 1.5 stop bit
176 LCR_SB2 // 2 stop bits
179 static unsigned char select_parity[] = {
181 LCR_PE, // Even parity
182 LCR_PO, // Odd parity
183 LCR_PM, // Mark parity
184 LCR_PS, // Space parity
187 // FIXME: calc all properly
188 // The Cogent board has a 3.6864 MHz crystal
189 static unsigned short select_baud[] = {