1 //==========================================================================
5 // Atmel AT91 (ARM) SPI driver
7 //==========================================================================
8 //####ECOSGPLCOPYRIGHTBEGIN####
9 // -------------------------------------------
10 // This file is part of eCos, the Embedded Configurable Operating System.
11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
13 // eCos is free software; you can redistribute it and/or modify it under
14 // the terms of the GNU General Public License as published by the Free
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19 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
22 // You should have received a copy of the GNU General Public License along
23 // with eCos; if not, write to the Free Software Foundation, Inc.,
24 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
26 // As a special exception, if other files instantiate templates or use macros
27 // or inline functions from this file, or you compile this file and link it
28 // with other works to produce a work based on this file, this file does not
29 // by itself cause the resulting work to be covered by the GNU General Public
30 // License. However the source code for this file must still be made available
31 // in accordance with section (3) of the GNU General Public License.
33 // This exception does not invalidate any other reasons why a work based on
34 // this file might be covered by the GNU General Public License.
35 // -------------------------------------------
36 //####ECOSGPLCOPYRIGHTEND####
37 //==========================================================================
38 //#####DESCRIPTIONBEGIN####
40 // Author(s): Savin Zlobec <savin@elatec.si>
43 //####DESCRIPTIONEND####
45 //==========================================================================
47 #include <pkgconf/hal.h>
48 #include <pkgconf/io_spi.h>
49 #include <pkgconf/devs_spi_arm_at91.h>
51 #include <cyg/infra/cyg_type.h>
52 #include <cyg/infra/cyg_ass.h>
53 #include <cyg/hal/hal_io.h>
54 #include <cyg/hal/hal_if.h>
55 #include <cyg/hal/hal_intr.h>
56 #include <cyg/hal/drv_api.h>
57 #include <cyg/io/spi.h>
58 #include <cyg/io/spi_at91.h>
59 #include <cyg/error/codes.h>
61 // -------------------------------------------------------------------------
62 static void spi_at91_init_bus(cyg_spi_at91_bus_t * bus);
64 static cyg_uint32 spi_at91_ISR(cyg_vector_t vector, cyg_addrword_t data);
66 static void spi_at91_DSR(cyg_vector_t vector,
70 static void spi_at91_transaction_begin(cyg_spi_device *dev);
72 static void spi_at91_transaction_transfer(cyg_spi_device *dev,
75 const cyg_uint8 *tx_data,
79 static void spi_at91_transaction_tick(cyg_spi_device *dev,
83 static void spi_at91_transaction_end(cyg_spi_device* dev);
85 static int spi_at91_get_config(cyg_spi_device *dev,
90 static int spi_at91_set_config(cyg_spi_device *dev,
95 // -------------------------------------------------------------------------
98 #ifdef CYGHWR_DEVS_SPI_ARM_AT91_BUS0
99 cyg_spi_at91_bus_t cyg_spi_at91_bus0 = {
100 .spi_bus.spi_transaction_begin = spi_at91_transaction_begin,
101 .spi_bus.spi_transaction_transfer = spi_at91_transaction_transfer,
102 .spi_bus.spi_transaction_tick = spi_at91_transaction_tick,
103 .spi_bus.spi_transaction_end = spi_at91_transaction_end,
104 .spi_bus.spi_get_config = spi_at91_get_config,
105 .spi_bus.spi_set_config = spi_at91_set_config,
106 .interrupt_number = CYGNUM_HAL_INTERRUPT_SPI,
108 #ifndef CYGDAT_DEVS_SPI_ARM_AT91_BUS0_NPCS0_NONE
110 .cs_gpio[0] = CYGDAT_DEVS_SPI_ARM_AT91_BUS0_NPCS0,
114 #ifndef CYGDAT_DEVS_SPI_ARM_AT91_BUS0_NPCS1_NONE
116 .cs_gpio[1] = CYGDAT_DEVS_SPI_ARM_AT91_BUS0_NPCS1,
120 #ifndef CYGDAT_DEVS_SPI_ARM_AT91_BUS0_NPCS2_NONE
122 .cs_gpio[2] = CYGDAT_DEVS_SPI_ARM_AT91_BUS0_NPCS2,
126 #ifndef CYGDAT_DEVS_SPI_ARM_AT91_BUS0_NPCS3_NONE
128 .cs_gpio[3] = CYGDAT_DEVS_SPI_ARM_AT91_BUS0_NPCS3,
134 CYG_SPI_DEFINE_BUS_TABLE(cyg_spi_at91_device_t, 0);
136 #ifdef CYGHWR_DEVS_SPI_ARM_AT91_BUS1
137 cyg_spi_at91_bus_t cyg_spi_at91_bus1 = {
138 .spi_bus.spi_transaction_begin = spi_at91_transaction_begin,
139 .spi_bus.spi_transaction_transfer = spi_at91_transaction_transfer,
140 .spi_bus.spi_transaction_tick = spi_at91_transaction_tick,
141 .spi_bus.spi_transaction_end = spi_at91_transaction_end,
142 .spi_bus.spi_get_config = spi_at91_get_config,
143 .spi_bus.spi_set_config = spi_at91_set_config,
144 .interrupt_number = CYGNUM_HAL_INTERRUPT_SPI1,
146 #ifndef CYGDAT_DEVS_SPI_ARM_AT91_BUS1_NPCS0_NONE
148 .cs_gpio[0] = CYGDAT_DEVS_SPI_ARM_AT91_BUS1_NPCS0,
152 #ifndef CYGDAT_DEVS_SPI_ARM_AT91_BUS1_NPCS1_NONE
154 .cs_gpio[1] = CYGDAT_DEVS_SPI_ARM_AT91_BUS1_NPCS1,
158 #ifndef CYGDAT_DEVS_SPI_ARM_AT91_BUS1_NPCS2_NONE
160 .cs_gpio[2] = CYGDAT_DEVS_SPI_ARM_AT91_BUS1_NPCS2,
164 #ifndef CYGDAT_DEVS_SPI_ARM_AT91_BUS1_NPCS3_NONE
166 .cs_gpio[3] = CYGDAT_DEVS_SPI_ARM_AT91_BUS1_NPCS3,
172 CYG_SPI_DEFINE_BUS_TABLE(cyg_spi_at91_device_t, 1);
174 // -------------------------------------------------------------------------
177 cyg_spi_at91_bus_init(void)
180 #ifdef CYGHWR_DEVS_SPI_ARM_AT91_BUS0
181 // NOTE: here we let the SPI controller control
182 // the data in, out and clock signals, but
183 // we need to handle the chip selects manually
184 // in order to achieve better chip select control
185 // in between transactions.
187 // Put SPI MISO, MOIS and SPCK pins into peripheral mode
188 HAL_ARM_AT91_PIO_CFG(AT91_SPI_SPCK);
189 HAL_ARM_AT91_PIO_CFG(AT91_SPI_MISO);
190 HAL_ARM_AT91_PIO_CFG(AT91_SPI_MOIS);
191 spi_at91_init_bus(&cyg_spi_at91_bus0);
193 #ifdef CYGHWR_DEVS_SPI_ARM_AT91_BUS1
194 // NOTE: here we let the SPI controller control
195 // the data in, out and clock signals, but
196 // we need to handle the chip selects manually
197 // in order to achieve better chip select control
198 // in between transactions.
200 // Put SPI MISO, MOIS and SPCK pins into peripheral mode
201 HAL_ARM_AT91_PIO_CFG(AT91_SPI1_SPCK);
202 HAL_ARM_AT91_PIO_CFG(AT91_SPI1_MISO);
203 HAL_ARM_AT91_PIO_CFG(AT91_SPI1_MOSI);
204 spi_at91_init_bus(&cyg_spi_at91_bus1);
208 // -------------------------------------------------------------------------
210 static void spi_at91_init_bus(cyg_spi_at91_bus_t * spi_bus)
213 // Create and attach SPI interrupt object
214 cyg_drv_interrupt_create(spi_bus->interrupt_number,
216 (cyg_addrword_t)spi_bus,
219 &spi_bus->spi_interrupt_handle,
220 &spi_bus->spi_interrupt);
222 cyg_drv_interrupt_attach(spi_bus->spi_interrupt_handle);
224 // Init transfer mutex and condition
225 cyg_drv_mutex_init(&spi_bus->transfer_mx);
226 cyg_drv_cond_init(&spi_bus->transfer_cond,
227 &spi_bus->transfer_mx);
230 spi_bus->transfer_end = true;
231 spi_bus->cs_up = false;
233 // Soft reset the SPI controller
234 HAL_WRITE_UINT32(spi_bus->base+AT91_SPI_CR, AT91_SPI_CR_SWRST);
236 // Configure SPI pins
239 // Put SPI chip select pins in IO output mode
240 for(ctr = 0;ctr<4;ctr++)
242 if(spi_bus->cs_en[ctr])
244 HAL_ARM_AT91_GPIO_CFG_DIRECTION(spi_bus->cs_gpio[ctr],AT91_PIN_OUT);
247 // Call upper layer bus init
248 CYG_SPI_BUS_COMMON_INIT(&spi_bus->spi_bus);
252 spi_at91_ISR(cyg_vector_t vector, cyg_addrword_t data)
255 cyg_spi_at91_bus_t * spi_bus = (cyg_spi_at91_bus_t *)data;
256 // Read the status register and disable
257 // the SPI int events that have occoured
259 HAL_READ_UINT32(spi_bus->base+AT91_SPI_SR, stat);
260 HAL_WRITE_UINT32(spi_bus->base+AT91_SPI_IDR, stat);
262 cyg_drv_interrupt_mask(vector);
263 cyg_drv_interrupt_acknowledge(vector);
265 return CYG_ISR_CALL_DSR;
269 spi_at91_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data)
271 cyg_spi_at91_bus_t *spi_bus = (cyg_spi_at91_bus_t *) data;
274 // Read the status register and
275 // check for transfer completition
277 HAL_READ_UINT32(spi_bus->base+AT91_SPI_SR, stat);
279 if((stat & AT91_SPI_SR_ENDRX) && (stat & AT91_SPI_SR_ENDTX))
282 spi_bus->transfer_end = true;
283 cyg_drv_cond_signal(&spi_bus->transfer_cond);
287 // Transfer still in progress - unmask the SPI
288 // int so we can get more SPI int events
289 cyg_drv_interrupt_unmask(vector);
294 spi_at91_calc_scbr(cyg_spi_at91_device_t *dev)
299 // Calculate SCBR from baud rate
301 scbr = CYGNUM_HAL_ARM_AT91_CLOCK_SPEED / (2*dev->cl_brate);
313 scbr = CYGNUM_HAL_ARM_AT91_CLOCK_SPEED / (64*dev->cl_brate);
326 dev->cl_scbr = (cyg_uint8)scbr;
330 dev->cl_scbr = (cyg_uint8)scbr;
338 spi_at91_set_npcs(cyg_spi_at91_bus_t *spi_bus,int val)
341 for(ctr=0;ctr<4;ctr++)
343 if(spi_bus->cs_en[ctr])
345 HAL_ARM_AT91_GPIO_PUT(spi_bus->cs_gpio[ctr], (val & (1<<ctr)));
351 spi_at91_start_transfer(cyg_spi_at91_device_t *dev)
353 cyg_spi_at91_bus_t *spi_bus = (cyg_spi_at91_bus_t *)dev->spi_device.spi_bus;
358 // Force minimal delay between two transfers - in case two transfers
359 // follow each other w/o delay, then we have to wait here in order for
360 // the peripheral device to detect cs transition from inactive to active.
361 CYGACC_CALL_IF_DELAY_US(dev->tr_bt_udly);
365 #ifdef CYGHWR_DEVS_SPI_ARM_AT91_PCSDEC
366 spi_at91_set_npcs(spi_bus,~dev->dev_num);
368 spi_at91_set_npcs(spi_bus,~(1<<dev->dev_num));
370 CYGACC_CALL_IF_DELAY_US(dev->cs_up_udly);
372 spi_bus->cs_up = true;
376 spi_at91_drop_cs(cyg_spi_at91_device_t *dev)
378 cyg_spi_at91_bus_t *spi_bus = (cyg_spi_at91_bus_t *)dev->spi_device.spi_bus;
385 CYGACC_CALL_IF_DELAY_US(dev->cs_dw_udly);
386 spi_at91_set_npcs(spi_bus,0x0F);
387 spi_bus->cs_up = false;
391 spi_at91_transfer(cyg_spi_at91_device_t *dev,
393 const cyg_uint8 *tx_data,
396 cyg_spi_at91_bus_t *spi_bus = (cyg_spi_at91_bus_t *)dev->spi_device.spi_bus;
398 // Since PDC transfer buffer counters are 16 bit long,
399 // we have to split longer transfers into chunks.
402 cyg_uint16 tr_count = count > 0xFFFF ? 0xFFFF : count;
404 // Set rx buf pointer and counter
407 HAL_WRITE_UINT32(spi_bus->base+AT91_SPI_RPR, (cyg_uint32)rx_data);
408 HAL_WRITE_UINT32(spi_bus->base+AT91_SPI_RCR, (cyg_uint32)tr_count);
411 // Set tx buf pointer and counter
412 HAL_WRITE_UINT32(spi_bus->base+AT91_SPI_TPR, (cyg_uint32)tx_data);
413 HAL_WRITE_UINT32(spi_bus->base+AT91_SPI_TCR, (cyg_uint32)tr_count);
416 HAL_WRITE_UINT32(spi_bus->base+AT91_SPI_PTCR,
417 AT91_SPI_PTCR_RXTEN | AT91_SPI_PTCR_TXTEN);
419 // Enable the SPI int events we are interested in
420 HAL_WRITE_UINT32(spi_bus->base+AT91_SPI_IER,
421 AT91_SPI_SR_ENDRX | AT91_SPI_SR_ENDTX);
423 cyg_drv_mutex_lock(&spi_bus->transfer_mx);
425 spi_bus->transfer_end = false;
427 // Unmask the SPI int
428 cyg_drv_interrupt_unmask(spi_bus->interrupt_number);
430 // Wait for its completition
433 while (!spi_bus->transfer_end)
434 cyg_drv_cond_wait(&spi_bus->transfer_cond);
436 cyg_drv_dsr_unlock();
438 cyg_drv_mutex_unlock(&spi_bus->transfer_mx);
444 // If rx buffer was NULL, then the PDC receiver data transfer
445 // was not started and we didn't wait for ENDRX, but only for
446 // ENDTX. Meaning that right now the last byte is being serialized
447 // over the line and when finished input data will appear in
448 // rx data reg. We have to wait for this to happen here, if we
449 // don't we'll get the last received byte as the first one in the
452 // FIXME: is there any better way to do this?
453 // If not, then precalculate this value.
454 val = 8000000/dev->cl_brate;
455 CYGACC_CALL_IF_DELAY_US(val > 1 ? val : 1);
457 // Clear the rx data reg
458 HAL_READ_UINT32(spi_bus->base+AT91_SPI_RDR, val);
461 // Adjust running variables
471 spi_at91_transfer_polled(cyg_spi_at91_device_t *dev,
473 const cyg_uint8 *tx_data,
477 cyg_spi_at91_bus_t *spi_bus = (cyg_spi_at91_bus_t *)dev->spi_device.spi_bus;
479 // Transmit and receive byte by byte
482 // Wait for transmit data register empty
485 HAL_READ_UINT32(spi_bus->base+AT91_SPI_SR, val);
486 } while ( !(val & AT91_SPI_SR_TDRE) );
488 // Send next byte over the wire
490 HAL_WRITE_UINT32(spi_bus->base+AT91_SPI_TDR, val);
492 // Wait for reveive data register full
495 HAL_READ_UINT32(spi_bus->base+AT91_SPI_SR, val);
496 } while ( !(val & AT91_SPI_SR_RDRF) );
498 // Store received byte
499 HAL_READ_UINT32(spi_bus->base+AT91_SPI_RDR, val);
505 // -------------------------------------------------------------------------
508 spi_at91_transaction_begin(cyg_spi_device *dev)
510 cyg_spi_at91_device_t *at91_spi_dev = (cyg_spi_at91_device_t *) dev;
511 cyg_spi_at91_bus_t *spi_bus =
512 (cyg_spi_at91_bus_t *)at91_spi_dev->spi_device.spi_bus;
515 if (!at91_spi_dev->init)
517 at91_spi_dev->init = true;
518 spi_at91_calc_scbr(at91_spi_dev);
521 // Configure SPI channel 0 - this is the only channel we
522 // use for all devices since we drive chip selects manually
524 val = AT91_SPI_CSR_BITS8;
526 if (1 == at91_spi_dev->cl_pol)
527 val |= AT91_SPI_CSR_CPOL;
529 if (1 == at91_spi_dev->cl_pha)
530 val |= AT91_SPI_CSR_NCPHA;
532 val |= AT91_SPI_CSR_SCBR(at91_spi_dev->cl_scbr);
534 HAL_WRITE_UINT32(spi_bus->base+AT91_SPI_CSR0, val);
537 HAL_WRITE_UINT32(AT91_PMC+AT91_PMC_PCER, 1<<spi_bus->interrupt_number);
539 // Enable the SPI controller
540 HAL_WRITE_UINT32(spi_bus->base+AT91_SPI_CR, AT91_SPI_CR_SPIEN);
542 /* As we are using this driver only in master mode with NPCS0
543 configured as GPIO instead of a peripheral pin, it is neccessary
544 for the Mode Failure detection to be switched off as this will
545 cause havoc with the driver */
547 // Put SPI bus into master mode
548 if (1 == at91_spi_dev->cl_div32) {
549 val = AT91_SPI_MR_MSTR | AT91_SPI_MR_DIV32;
550 #ifdef AT91_SPI_MR_MODFDIS
551 val |= AT91_SPI_MR_MODFDIS;
553 HAL_WRITE_UINT32(spi_bus->base+AT91_SPI_MR, val);
555 val = AT91_SPI_MR_MSTR;
556 #ifdef AT91_SPI_MR_MODFDIS
557 val |= AT91_SPI_MR_MODFDIS;
559 HAL_WRITE_UINT32(spi_bus->base+AT91_SPI_MR, val);
564 spi_at91_transaction_transfer(cyg_spi_device *dev,
567 const cyg_uint8 *tx_data,
571 cyg_spi_at91_device_t *at91_spi_dev = (cyg_spi_at91_device_t *) dev;
573 // Select the device if not already selected
574 spi_at91_start_transfer(at91_spi_dev);
576 // Perform the transfer
578 spi_at91_transfer_polled(at91_spi_dev, count, tx_data, rx_data);
580 spi_at91_transfer(at91_spi_dev, count, tx_data, rx_data);
582 // Deselect the device if requested
584 spi_at91_drop_cs(at91_spi_dev);
588 spi_at91_transaction_tick(cyg_spi_device *dev,
592 const cyg_uint32 zeros[10] = { 0,0,0,0,0,0,0,0,0,0 };
594 cyg_spi_at91_device_t *at91_spi_dev = (cyg_spi_at91_device_t *) dev;
596 // Transfer count zeros to the device - we don't touch the
597 // chip select, the device could be selected or deselected.
598 // It is up to the device driver to decide in wich state the
599 // device will be ticked.
603 int tcnt = count > 40 ? 40 : count;
606 spi_at91_transfer_polled(at91_spi_dev, tcnt,
607 (const cyg_uint8 *) zeros, NULL);
609 spi_at91_transfer(at91_spi_dev, tcnt,
610 (const cyg_uint8 *) zeros, NULL);
617 spi_at91_transaction_end(cyg_spi_device* dev)
619 cyg_spi_at91_device_t * at91_spi_dev = (cyg_spi_at91_device_t *)dev;
620 cyg_spi_at91_bus_t *spi_bus =
621 (cyg_spi_at91_bus_t *)at91_spi_dev->spi_device.spi_bus;
623 // Disable the SPI controller
624 HAL_WRITE_UINT32(spi_bus->base+AT91_SPI_CR, AT91_SPI_CR_SPIDIS);
627 HAL_WRITE_UINT32(AT91_PMC+AT91_PMC_PCDR,1<<spi_bus->interrupt_number);
629 spi_at91_drop_cs((cyg_spi_at91_device_t *) dev);
633 spi_at91_get_config(cyg_spi_device *dev,
638 cyg_spi_at91_device_t *at91_spi_dev = (cyg_spi_at91_device_t *) dev;
642 case CYG_IO_GET_CONFIG_SPI_CLOCKRATE:
644 if (*len != sizeof(cyg_uint32))
648 cyg_uint32 *cl_brate = (cyg_uint32 *)buf;
649 *cl_brate = at91_spi_dev->cl_brate;
660 spi_at91_set_config(cyg_spi_device *dev,
665 cyg_spi_at91_device_t *at91_spi_dev = (cyg_spi_at91_device_t *) dev;
669 case CYG_IO_SET_CONFIG_SPI_CLOCKRATE:
671 if (*len != sizeof(cyg_uint32))
675 cyg_uint32 cl_brate = *((cyg_uint32 *)buf);
676 cyg_uint32 old_cl_brate = at91_spi_dev->cl_brate;
678 at91_spi_dev->cl_brate = cl_brate;
680 if (!spi_at91_calc_scbr(at91_spi_dev))
682 at91_spi_dev->cl_brate = old_cl_brate;
683 spi_at91_calc_scbr(at91_spi_dev);
695 // -------------------------------------------------------------------------