1 //==========================================================================
5 // SPI support on Freescale MXC platforms
7 //==========================================================================
8 //####ECOSGPLCOPYRIGHTBEGIN####
9 // -------------------------------------------
10 // This file is part of eCos, the Embedded Configurable Operating System.
11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
13 // eCos is free software; you can redistribute it and/or modify it under
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19 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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24 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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27 // or inline functions from this file, or you compile this file and link it
28 // with other works to produce a work based on this file, this file does not
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30 // License. However the source code for this file must still be made available
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37 // at http://sources.redhat.com/ecos/ecos-license/
38 // -------------------------------------------
39 //####ECOSGPLCOPYRIGHTEND####
40 //==========================================================================
41 //#####DESCRIPTIONBEGIN####
43 // Author(s): Kevin Zhang <k.zhang@freescale.com>
49 //####DESCRIPTIONEND####
51 //==========================================================================
56 #define SPI_RX_REG_OFF 0x0
57 #define SPI_TX_REG_OFF 0x4
58 #define SPI_CTRL_REG_OFF 0x8
60 #if defined(MXC_SPI_VER_0_4)
61 #define SPI_INT_CTRL_REG_OFF 0xC
62 #define SPI_DMA_REG_OFF 0x10
63 #define SPI_INT_STAT_REG_OFF 0x14
64 #define SPI_PERIOD_REG_OFF 0x18
65 #define SPI_TEST_REG_OFF 0x1C
67 #define SPI_INT_STAT_RR (1 << 3)
69 #define SPI_CTRL_REG_XCH_BIT (1 << 2)
70 #define SPI_CTRL_REG_RATE_SH 16 // start from bit 16
71 #define SPI_CTRL_REG_RATE_WD 3 // 3-bit width
73 #define SPI_CTRL_REG_BIT_COUNT32 (0x1F << 8) // 32-bit xfer
74 #define SPI_CTRL_REG_BIT_COUNT23 (0x16 << 8) // 23-bit xfer
75 #define SPI_CTRL_CS0 (0 << 24)
76 #define SPI_CTRL_CS1 (1 << 24)
77 #define SPI_CTRL_CS2 (2 << 24)
78 #define SPI_CTRL_CS3 (3 << 24)
79 #define SPI_CTRL_CS_MASK (3 << 24)
80 #define SPI_CTRL_SSPOL_HIGH (1 << 7)
81 #define SPI_CTRL_SSCTL_SET (1 << 6)
82 #define SPI_CTRL_SCLK_POL_LOW (1 << 4)
83 #define SPI_CTRL_MODE_MASTER (1 << 1)
84 #define SPI_CTRL_EN (1 << 0)
85 #define SPI_TEST_REG_RXCNT_OFFSET 4
86 #define SPI_TEST_REG_RXCNT_MASK (0xF << 4)
88 #elif defined(MXC_SPI_VER_0_7)
89 #define SPI_INT_CTRL_REG_OFF 0xC
90 #define SPI_DMA_REG_OFF 0x10
91 #define SPI_INT_STAT_REG_OFF 0x14
92 #define SPI_PERIOD_REG_OFF 0x18
93 #define SPI_TEST_REG_OFF 0x1C
95 #define SPI_INT_STAT_RR (1 << 3)
97 #define SPI_CTRL_REG_XCH_BIT (1 << 2)
98 #define SPI_CTRL_REG_RATE_SH 16 // start from bit 16
99 #define SPI_CTRL_REG_RATE_WD 3 // 3-bit width
101 #define SPI_CTRL_REG_BIT_COUNT46 (0x2D << 20) // 48-bit xfer
102 #define SPI_CTRL_REG_BIT_COUNT32 (0x1F << 20) // 32-bit xfer
103 #define SPI_CTRL_REG_BIT_COUNT23 (0x16 << 20) // 23-bit xfer
104 #define SPI_CTRL_CS0 (0 << 12)
105 #define SPI_CTRL_CS1 (1 << 12)
106 #define SPI_CTRL_CS2 (2 << 12)
107 #define SPI_CTRL_CS3 (3 << 12)
108 #define SPI_CTRL_CS_MASK (3 << 12)
109 #define SPI_CTRL_SSPOL_HIGH (1 << 7)
110 #define SPI_CTRL_SSCTL_SET (1 << 6)
111 #define SPI_CTRL_SCLK_POL_LOW (1 << 4)
112 #define SPI_CTRL_MODE_MASTER (1 << 1)
113 #define SPI_CTRL_EN (1 << 0)
114 #define SPI_TEST_REG_RXCNT_OFFSET 4
115 #define SPI_TEST_REG_RXCNT_MASK (0xF << 4)
118 #elif defined(MXC_SPI_VER_2_3)
119 #define SPI_CONFIG_REG_OFF 0xC
120 #define SPI_INT_CTRL_REG_OFF 0x10
121 #define SPI_DMA_REG_OFF 0x14
122 #define SPI_INT_STAT_REG_OFF 0x18
123 #define SPI_PERIOD_REG_OFF 0x1C
124 #define SPI_TEST_REG_OFF 0x20
126 #define SPI_INT_STAT_RR (1 << 3)
128 #define SPI_CTRL_REG_XCH_BIT (1 << 2)
129 #define SPI_CTRL_REG_RATE_SH 12 // start from bit 12
130 #define SPI_CTRL_REG_RATE_WD 4 // 3-bit width
131 #define SPI_CTRL_REG_BIT_COUNT32 (0x1F << 20) // 32-bit xfer
132 #define SPI_CTRL_REG_BIT_COUNT23 (0x16 << 20) // 23-bit xfer
133 #define SPI_CTRL_REG_BIT_COUNT46 (0x2D << 20) // 46-bit xfer
134 #define SPI_CTRL_CS0 (0 << 18)
135 #define SPI_CTRL_CS1 (1 << 18)
136 #define SPI_CTRL_CS2 (2 << 18)
137 #define SPI_CTRL_CS3 (3 << 18)
138 #define SPI_CTRL_CS_MASK (3 << 18)
139 #define SPI_CTRL_MODE_MASTER_0 (1 << 4)
140 #define SPI_CTRL_MODE_MASTER_1 (1 << 5)
141 #define SPI_CTRL_MODE_MASTER_2 (1 << 6)
142 #define SPI_CTRL_MODE_MASTER_3 (1 << 7)
143 #define SPI_CTRL_EN (1 << 0)
145 #define SPI_CFG_SS0_POL_HIGH (1 << 12)
146 #define SPI_CFG_SS1_POL_HIGH (1 << 13)
147 #define SPI_CFG_SS2_POL_HIGH (1 << 14)
148 #define SPI_CFG_SS3_POL_HIGH (1 << 15)
149 #define SPI_CFG_SS0_POL_LOW (0 << 12)
150 #define SPI_CFG_SS1_POL_LOW (0 << 13)
151 #define SPI_CFG_SS2_POL_LOW (0 << 14)
152 #define SPI_CFG_SS3_POL_LOW (0 << 15)
154 #define SPI_TEST_REG_RXCNT_OFFSET 8
155 #define SPI_TEST_REG_RXCNT_MASK (0x7F << 8)
158 #define SPI_INT_CTRL_REG_OFF 0xC
159 #define SPI_INT_STAT_REG_OFF 0xC
160 #define SPI_TEST_REG_OFF 0x10
161 #define SPI_PERIOD_REG_OFF 0x14
162 #define SPI_DMA_REG_OFF 0x18
163 #define SPI_RESET_REG_OFF 0x1C
165 #define SPI_INT_STAT_RR (1 << 4)
167 #define SPI_CTRL_REG_XCH_BIT (1 << 9)
168 #define SPI_CTRL_REG_RATE_SH 14 // start from bit 14
169 #define SPI_CTRL_REG_RATE_WD 5 // 5-bit width
171 #define SPI_CTRL_BURST_EN (1 << 23)
172 #define SPI_CTRL_SDHC_SPI_EN (1 << 22)
173 #define SPI_CTRL_SWAP_EN (1 << 21)
174 #define SPI_CTRL_CS0 (0 << 19)
175 #define SPI_CTRL_CS1 (1 << 19)
176 #define SPI_CTRL_CS2 (2 << 19)
177 #define SPI_CTRL_CS_MASK (3 << 19)
178 #define SPI_CTRL_SSPOL_HIGH (1 << 8)
179 #define SPI_CTRL_SSCTL_SET (1 << 7)
180 #define SPI_CTRL_SCLK_POL_LOW (1 << 5)
181 #define SPI_CTRL_REG_BIT_COUNT32 0x1F // 32-bit xfer
182 #define SPI_CTRL_REG_BIT_COUNT23 0x16 // 23-bit xfer
183 #define SPI_CTRL_MODE_MASTER (1 << 11)
184 #define SPI_CTRL_EN (1 << 10)
185 #define SPI_TEST_REG_RXCNT_OFFSET 4
186 #define SPI_TEST_REG_RXCNT_MASK (0xF << 4)
190 int spi_init(unsigned int base, unsigned int baud, unsigned int ctrl_val);
191 unsigned int pmic_reg(unsigned int reg, unsigned int val, unsigned int write);
192 unsigned int spi_xchg_single(unsigned int data, unsigned int base);
195 unsigned int spi_cpld_xchg_single(unsigned int data, unsigned int data1, unsigned int base);
196 unsigned int cpld_reg(unsigned int reg, unsigned int val, unsigned int read);
197 unsigned int cpld_reg_xfer(unsigned int reg, unsigned int val, unsigned int read);
198 #endif /* CPLD_SPI_BASE */
200 #endif /* __MXC_SPI_H__ */