1 //==========================================================================
3 // devs/watchdog/arm/aeb/watchdog_aeb.cxx
5 // Watchdog implementation for ARM AEB1 board (SHARP LH77790 CPU)
7 //==========================================================================
8 //####ECOSGPLCOPYRIGHTBEGIN####
9 // -------------------------------------------
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38 // -------------------------------------------
39 //####ECOSGPLCOPYRIGHTEND####
40 //==========================================================================
41 //#####DESCRIPTIONBEGIN####
44 // Contributors: jskov
46 // Purpose: Watchdog class implementation
47 // Description: Contains an implementation of the Watchdog class for use
48 // with the SHARP LH77790 watchdog timer.
50 //####DESCRIPTIONEND####
52 //==========================================================================
54 #include <pkgconf/system.h> // system configuration file
55 #include <pkgconf/watchdog.h> // configuration for this package
56 #include <pkgconf/kernel.h> // kernel config
58 #include <cyg/infra/cyg_trac.h> // tracing macros
59 #include <cyg/kernel/instrmnt.h> // instrumentation
61 #include <cyg/hal/hal_io.h> // IO register access
63 #include <cyg/io/watchdog.hxx> // watchdog API
65 // -------------------------------------------------------------------------
66 // Register definitions
67 #define CYGARC_REG_WATCHDOG_BASE 0xFFFFAC00
68 #define CYGARC_REG_WATCHDOG_WDCTLR (CYGARC_REG_WATCHDOG_BASE+0x30)
69 #define CYGARC_REG_WATCHDOG_WDCNTR (CYGARC_REG_WATCHDOG_BASE+0x34)
71 // Control register bits
72 #define CYGARC_REG_WATCHDOG_WDCTLR_EN 0x01 // enable
73 #define CYGARC_REG_WATCHDOG_WDCTLR_RSP_NMF 0x00 // non-maskable fiq
74 #define CYGARC_REG_WATCHDOG_WDCTLR_RSP_ER 0x04 // external reset
75 #define CYGARC_REG_WATCHDOG_WDCTLR_RSP_SR 0x06 // system reset
76 #define CYGARC_REG_WATCHDOG_WDCTLR_FRZ 0x08 // lock enable bit
77 #define CYGARC_REG_WATCHDOG_WDCTLR_TOP_MASK 0x70 // time out period
79 #define CYGARC_REG_WATCHDOG_WDCTLR_TOP_17 0x00 // 2^17
80 #define CYGARC_REG_WATCHDOG_WDCTLR_TOP_17_P 5242880 // = 5.2ms
82 #define CYGARC_REG_WATCHDOG_WDCTLR_TOP_25 0x40 // 2^25
83 #define CYGARC_REG_WATCHDOG_WDCTLR_TOP_25_P 1342177300 // = 1.3421773s
86 // -------------------------------------------------------------------------
90 Cyg_Watchdog::init_hw(void)
92 CYG_REPORT_FUNCTION();
96 resolution = CYGARC_REG_WATCHDOG_WDCTLR_TOP_25_P;
101 // -------------------------------------------------------------------------
102 // Start the watchdog running.
105 Cyg_Watchdog::start()
107 CYG_REPORT_FUNCTION();
109 // Clear the watchdog counter.
110 HAL_WRITE_UINT32(CYGARC_REG_WATCHDOG_WDCNTR, 0);
112 // Enable the watchdog (and lock/FRZ it).
113 HAL_WRITE_UINT8(CYGARC_REG_WATCHDOG_WDCTLR,
114 (CYGARC_REG_WATCHDOG_WDCTLR_TOP_25
115 | CYGARC_REG_WATCHDOG_WDCTLR_FRZ
116 | CYGARC_REG_WATCHDOG_WDCTLR_RSP_SR
117 | CYGARC_REG_WATCHDOG_WDCTLR_EN));
122 // -------------------------------------------------------------------------
123 // Reset watchdog timer. This needs to be called regularly to prevent
124 // the watchdog firing.
127 Cyg_Watchdog::reset()
129 CYG_REPORT_FUNCTION();
131 HAL_WRITE_UINT32(CYGARC_REG_WATCHDOG_WDCNTR, 0);
137 // -------------------------------------------------------------------------
138 // Action which will do a board reset. Application can register this
139 // action to get a board reset on watchdog timeout.
142 Cyg_Watchdog::reset_action(void)
144 CYG_REPORT_FUNCTION();
146 // Clear the watchdog counter.
147 HAL_WRITE_UINT32(CYGARC_REG_WATCHDOG_WDCNTR, 0);
149 // Enable the watchdog with the smallest timeout.
150 HAL_WRITE_UINT8(CYGARC_REG_WATCHDOG_WDCTLR,
151 (CYGARC_REG_WATCHDOG_WDCTLR_TOP_17
152 | CYGARC_REG_WATCHDOG_WDCTLR_FRZ
153 | CYGARC_REG_WATCHDOG_WDCTLR_RSP_SR
154 | CYGARC_REG_WATCHDOG_WDCTLR_EN));
160 // -------------------------------------------------------------------------
161 // EOF watchdog_aeb.cxx