1 //==========================================================================
3 // devs/watchdog/sh/sh3/watchdog_sh3.cxx
5 // Watchdog implementation for Hitachi SH CPUs
7 //==========================================================================
8 //####ECOSGPLCOPYRIGHTBEGIN####
9 // -------------------------------------------
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27 // or inline functions from this file, or you compile this file and link it
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38 // -------------------------------------------
39 //####ECOSGPLCOPYRIGHTEND####
40 //==========================================================================
41 //#####DESCRIPTIONBEGIN####
44 // Contributors: jskov
46 // Purpose: Watchdog class implementation
47 // Description: Contains an implementation of the Watchdog class for use
48 // with the Hitachi SH watchdog timer.
50 //####DESCRIPTIONEND####
52 //==========================================================================
54 #include <pkgconf/system.h> // system configuration file
55 #include <pkgconf/watchdog.h> // configuration for this package
56 #include <pkgconf/kernel.h> // kernel config
58 #include <cyg/infra/cyg_trac.h> // tracing macros
59 #include <cyg/kernel/instrmnt.h> // instrumentation
61 #include <cyg/hal/hal_io.h> // IO register access
62 #include <cyg/hal/sh_regs.h> // watchdog register definitions
64 #include <cyg/io/watchdog.hxx> // watchdog API
66 // -------------------------------------------------------------------------
70 Cyg_Watchdog::init_hw(void)
72 CYG_REPORT_FUNCTION();
74 // No hardware init needed.
76 resolution = CYGARC_REG_WTCSR_PERIOD;
81 // -------------------------------------------------------------------------
82 // Start the watchdog running.
87 CYG_REPORT_FUNCTION();
89 // Init the watchdog timer (note: 8 bit reads, 16 bit writes)
91 // First disable without changing other bits.
92 HAL_READ_UINT8(CYGARC_REG_WTCSR, csr);
93 csr |= CYGARC_REG_WTCSR_WRITE;
94 csr &= ~CYGARC_REG_WTCSR_TME;
95 HAL_WRITE_UINT16(CYGARC_REG_WTCSR, csr);
96 // Then set control bits and clear counter.
97 csr = (CYGARC_REG_WTCSR_WRITE
98 |CYGARC_REG_WTCSR_WT_IT
99 |CYGARC_REG_WTCSR_CKSx_SETTING);
100 HAL_WRITE_UINT16(CYGARC_REG_WTCSR, csr);
101 HAL_WRITE_UINT16(CYGARC_REG_WTCNT, CYGARC_REG_WTCNT_WRITE);
102 // Finally enable timer.
103 csr |= CYGARC_REG_WTCSR_TME;
104 HAL_WRITE_UINT16(CYGARC_REG_WTCSR, csr);
109 // -------------------------------------------------------------------------
110 // Reset watchdog timer. This needs to be called regularly to prevent
111 // the watchdog firing.
114 Cyg_Watchdog::reset()
116 CYG_REPORT_FUNCTION();
118 HAL_WRITE_UINT16(CYGARC_REG_WTCNT, CYGARC_REG_WTCNT_WRITE);
124 // -------------------------------------------------------------------------
125 // Trigger the watchdog as if the timer had expired.
128 Cyg_Watchdog::action_reset(void)
130 CYG_REPORT_FUNCTION();
134 HAL_WRITE_UINT16(CYGARC_REG_WTCNT, CYGARC_REG_WTCNT_WRITE|0xfe);
140 // -------------------------------------------------------------------------
141 // EOF watchdog_sh3.cxx