packages/hal/arm/aeb/v2_0/src/aeb_misc.c

   1 //==========================================================================
   2 //
   3 //      aeb_misc.c
   4 //
   5 //      HAL misc board support code for ARM AEB-1
   6 //
   7 //==========================================================================
   8 //####ECOSGPLCOPYRIGHTBEGIN####
   9 // -------------------------------------------
  10 // This file is part of eCos, the Embedded Configurable Operating System.
  11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
  12 //
  13 // eCos is free software; you can redistribute it and/or modify it under
  14 // the terms of the GNU General Public License as published by the Free
  15 // Software Foundation; either version 2 or (at your option) any later version.
  16 //
  17 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
  18 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
  19 // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  20 // for more details.
  21 //
  22 // You should have received a copy of the GNU General Public License along
  23 // with eCos; if not, write to the Free Software Foundation, Inc.,
  24 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  25 //
  26 // As a special exception, if other files instantiate templates or use macros
  27 // or inline functions from this file, or you compile this file and link it
  28 // with other works to produce a work based on this file, this file does not
  29 // by itself cause the resulting work to be covered by the GNU General Public
  30 // License. However the source code for this file must still be made available
  31 // in accordance with section (3) of the GNU General Public License.
  32 //
  33 // This exception does not invalidate any other reasons why a work based on
  34 // this file might be covered by the GNU General Public License.
  35 //
  36 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
  37 // at http://sources.redhat.com/ecos/ecos-license/
  38 // -------------------------------------------
  39 //####ECOSGPLCOPYRIGHTEND####
  40 //==========================================================================
  41 //#####DESCRIPTIONBEGIN####
  42 //
  43 // Author(s):    gthomas
  44 // Contributors: gthomas
  45 // Date:         1999-02-20
  46 // Purpose:      HAL board support
  47 // Description:  Implementations of HAL board interfaces
  48 //
  49 //####DESCRIPTIONEND####
  50 //
  51 //========================================================================*/
  52
  53 #include <pkgconf/hal.h>
  54
  55 #include <cyg/infra/cyg_type.h>         // base types
  56 #include <cyg/infra/cyg_trac.h>         // tracing macros
  57 #include <cyg/infra/cyg_ass.h>          // assertion macros
  58
  59 #include <cyg/hal/hal_io.h>             // IO macros
  60 #include <cyg/hal/hal_arch.h>           // Register state info
  61 #include <cyg/hal/hal_diag.h>
  62 #include <cyg/hal/hal_intr.h>           // necessary?
  63 #include <cyg/hal/hal_cache.h>
  64 #include <cyg/hal/hal_if.h>             // calling interface
  65 #include <cyg/hal/hal_misc.h>           // helper functions
  66 #ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
  67 #include <cyg/hal/drv_api.h>            // HAL ISR support
  68 #endif
  69
  70 /*------------------------------------------------------------------------*/
  71 // On-board timer
  72 /*------------------------------------------------------------------------*/
  73
  74 // Timer registers
  75 #define CYG_DEVICE_TIMER0       ((volatile cyg_uint8  *)0xFFFF1800)
  76 #define CYG_DEVICE_TIMER1       ((volatile cyg_uint8  *)0xFFFF1804)
  77 #define CYG_DEVICE_TIMER2       ((volatile cyg_uint8  *)0xFFFF1808)
  78 #define CYG_DEVICE_TIMER_CTL    ((volatile cyg_uint8  *)0xFFFF180C)
  79 #define CYG_DEVICE_IOCR         ((volatile cyg_uint32 *)0xFFFFA410)
  80 #define CYG_DEVICE_CPM_PCSR     ((volatile cyg_uint32 *)0xFFFFAC04)
  81 #define CYG_DEVICE_CPM_CT0CCR   ((volatile cyg_uint32 *)0xFFFFAC18)
  82 #define CYG_DEVICE_CPM_CT1CCR   ((volatile cyg_uint32 *)0xFFFFAC1C)
  83 #define CYG_DEVICE_CPM_CT2CCR   ((volatile cyg_uint32 *)0xFFFFAC20)
  84
  85 #define IOCR_CT0G               (0x3<<9)
  86 #define IOCR_CT0G_EXTERNAL      (0x0<<9)
  87 #define IOCR_CT0G_PWM0          (0x1<<9)
  88 #define IOCR_CT0G_LOW           (0x2<<9)
  89 #define IOCR_CT0G_HIGH          (0x3<<9)
  90
  91 #define IOCR_CT1G               (0x3<<11)
  92 #define IOCR_CT1G_EXTERNAL      (0x0<<11)
  93 #define IOCR_CT1G_PWM0          (0x1<<11)
  94 #define IOCR_CT1G_LOW           (0x2<<11)
  95 #define IOCR_CT1G_HIGH          (0x3<<11)
  96
  97 #define IOCR_CT2G               (0x3<<13)
  98 #define IOCR_CT2G_EXTERNAL      (0x0<<13)
  99 #define IOCR_CT2G_PWM0          (0x1<<13)
 100 #define IOCR_CT2G_LOW           (0x2<<13)
 101 #define IOCR_CT2G_HIGH          (0x3<<13)
 102
 103 #define TIMER_CTL_TYPE          (0x1<<0)
 104 #define TIMER_CTL_TYPE_BIN      (0x0<<0)
 105 #define TIMER_CTL_TYPE_BCD      (0x1<<0)
 106 #define TIMER_CTL_MODE          (0x7<<1)
 107 #define TIMER_CTL_MODE_IOTC     (0x0<<1) // Interrupt on terminal count
 108 #define TIMER_CTL_MODE_HROS     (0x1<<1) // Hardware retriggerable one-shot
 109 #define TIMER_CTL_MODE_RG       (0x2<<1) // Rate generator
 110 #define TIMER_CTL_MODE_SWG      (0x3<<1) // Square-wave generator
 111 #define TIMER_CTL_MODE_STS      (0x4<<1) // Software triggered strobe
 112 #define TIMER_CTL_MODE_HTS      (0x5<<1) // Hardware triggered strobe
 113 #define TIMER_CTL_RW            (0x3<<4)
 114 #define TIMER_CTL_RW_LATCH      (0x0<<4) // Counter latch
 115 #define TIMER_CTL_RW_LSB        (0x1<<4)
 116 #define TIMER_CTL_RW_MSB        (0x2<<4)
 117 #define TIMER_CTL_RW_BOTH       (0x3<<4)
 118 #define TIMER_CTL_SC            (0x3<<6)
 119 #define TIMER_CTL_SC_CTR0       (0x0<<6)
 120 #define TIMER_CTL_SC_CTR1       (0x1<<6)
 121 #define TIMER_CTL_SC_CTR2       (0x2<<6)
 122 #define TIMER_CTL_SC_RBC        (0x3<<6)
 123
 124 // Interrupt controller registers
 125 #define CYG_DEVICE_ICTL_ICR0    ((volatile cyg_uint32 *)0xFFFFA800)
 126 #define CYG_DEVICE_ICTL_ICR1    ((volatile cyg_uint32 *)0xFFFFA804)
 127 #define CYG_DEVICE_ICTL_ICLR    ((volatile cyg_uint32 *)0xFFFFA808)
 128 #define CYG_DEVICE_ICTL_IRQER   ((volatile cyg_uint32 *)0xFFFFA80C)
 129 #define CYG_DEVICE_ICTL_FIQER   ((volatile cyg_uint32 *)0xFFFFA810)
 130 #define CYG_DEVICE_ICTL_IRQSR   ((volatile cyg_uint32 *)0xFFFFA814)
 131 #define CYG_DEVICE_ICTL_FIQSR   ((volatile cyg_uint32 *)0xFFFFA818)
 132 #define CYG_DEVICE_ICTL_IPR     ((volatile cyg_uint32 *)0xFFFFA81C)
 133
 134 #define ICTL_ICR0_CH0           (0x3<<0)
 135 #define ICTL_ICR0_CH0_HL        (0x1<<0)
 136 #define ICTL_ICR0_CH0_HL_AL     (0x0<<0)  // Active low
 137 #define ICTL_ICR0_CH0_HL_AH     (0x1<<0)  // Active high
 138 #define ICTL_ICR0_CH0_EL        (0x2<<0)
 139 #define ICTL_ICR0_CH0_EL_LT     (0x0<<0)  // Level triggered
 140 #define ICTL_ICR0_CH0_EL_ET     (0x2<<0)  // Edge triggered
 141 #define ICTL_ICR0_CH1           (0x3<<2)
 142 #define ICTL_ICR0_CH1_HL        (0x1<<2)
 143 #define ICTL_ICR0_CH1_HL_AL     (0x0<<2)  // Active low
 144 #define ICTL_ICR0_CH1_HL_AH     (0x1<<2)  // Active high
 145 #define ICTL_ICR0_CH1_EL        (0x2<<2)
 146 #define ICTL_ICR0_CH1_EL_LT     (0x0<<2)  // Level triggered
 147 #define ICTL_ICR0_CH1_EL_ET     (0x2<<2)  // Edge triggered
 148 #define ICTL_ICR0_CH2           (0x3<<4)
 149 #define ICTL_ICR0_CH2_HL        (0x1<<4)
 150 #define ICTL_ICR0_CH2_HL_AL     (0x0<<4)  // Active low
 151 #define ICTL_ICR0_CH2_HL_AH     (0x1<<4)  // Active high
 152 #define ICTL_ICR0_CH2_EL        (0x2<<4)
 153 #define ICTL_ICR0_CH2_EL_LT     (0x0<<4)  // Level triggered
 154 #define ICTL_ICR0_CH2_EL_ET     (0x2<<4)  // Edge triggered
 155 #define ICTL_ICR0_CH3           (0x3<<6)
 156 #define ICTL_ICR0_CH3_HL        (0x1<<6)
 157 #define ICTL_ICR0_CH3_HL_AL     (0x0<<6)  // Active low
 158 #define ICTL_ICR0_CH3_HL_AH     (0x1<<6)  // Active high
 159 #define ICTL_ICR0_CH3_EL        (0x2<<6)
 160 #define ICTL_ICR0_CH3_EL_LT     (0x0<<6)  // Level triggered
 161 #define ICTL_ICR0_CH3_EL_ET     (0x2<<6)  // Edge triggered
 162 #define ICTL_ICR0_CH4           (0x3<<8)
 163 #define ICTL_ICR0_CH4_HL        (0x1<<8)
 164 #define ICTL_ICR0_CH4_HL_AL     (0x0<<8)  // Active low
 165 #define ICTL_ICR0_CH4_HL_AH     (0x1<<8)  // Active high
 166 #define ICTL_ICR0_CH4_EL        (0x2<<8)
 167 #define ICTL_ICR0_CH4_EL_LT     (0x0<<8)  // Level triggered
 168 #define ICTL_ICR0_CH4_EL_ET     (0x2<<8)  // Edge triggered
 169 #define ICTL_ICR0_CH5           (0x3<<10)
 170 #define ICTL_ICR0_CH5_HL        (0x1<<10)
 171 #define ICTL_ICR0_CH5_HL_AL     (0x0<<10)  // Active low
 172 #define ICTL_ICR0_CH5_HL_AH     (0x1<<10)  // Active high
 173 #define ICTL_ICR0_CH5_EL        (0x2<<10)
 174 #define ICTL_ICR0_CH5_EL_LT     (0x0<<10)  // Level triggered
 175 #define ICTL_ICR0_CH5_EL_ET     (0x2<<10)  // Edge triggered
 176 #define ICTL_ICR1_CH6           (0x1<<0)
 177 #define ICTL_ICR1_CH6_HL        (0x1<<0)
 178 #define ICTL_ICR1_CH6_HL_AL     (0x0<<0)  // Active low
 179 #define ICTL_ICR1_CH6_HL_AH     (0x1<<0)  // Active high
 180 #define ICTL_ICR1_CH7           (0x1<<1)
 181 #define ICTL_ICR1_CH7_HL        (0x1<<1)
 182 #define ICTL_ICR1_CH7_HL_AL     (0x0<<1)  // Active low
 183 #define ICTL_ICR1_CH7_HL_AH     (0x1<<1)  // Active high
 184 #define ICTL_ICR1_CH8           (0x1<<2)
 185 #define ICTL_ICR1_CH8_HL        (0x1<<2)
 186 #define ICTL_ICR1_CH8_HL_AL     (0x0<<2)  // Active low
 187 #define ICTL_ICR1_CH8_HL_AH     (0x1<<2)  // Active high
 188
 189 // Clock control registers
 190 #define PCSR_CT0CS              (1<<3)
 191 #define PCSR_CT1CS              (1<<4)
 192 #define PCSR_CT2CS              (1<<5)
 193 #define CT_X16                  16
 194
 195 #undef _TIMERS_TESTING
 196 #ifdef _TIMERS_TESTING
 197 static void aeb_setup_timer1(cyg_uint32 period);
 198 #endif
 199
 200 static cyg_uint32 _period;
 201
 202 #ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
 203 static cyg_interrupt abort_interrupt;
 204 static cyg_handle_t  abort_interrupt_handle;
 205
 206 // This ISR is called only for the Abort button interrupt
 207 static int
 208 aeb_abort_isr(cyg_vector_t vector, cyg_addrword_t data, HAL_SavedRegisters *regs)
 209 {
 210     cyg_hal_user_break((CYG_ADDRWORD*)regs);
 211     cyg_drv_interrupt_acknowledge(CYGNUM_HAL_INTERRUPT_EXT0);
 212     return 0;  // No need to run DSR
 213 }
 214 #endif
 215
 216 void hal_clock_initialize(cyg_uint32 period)
 217 {
 218     cyg_uint32 iocr;
 219
 220     // Set counter GATE input low (0) to halt counter while it's being setup
 221     HAL_READ_UINT32(CYG_DEVICE_IOCR, iocr);
 222     iocr = (iocr & ~IOCR_CT0G) | IOCR_CT0G_LOW;
 223     HAL_WRITE_UINT32(CYG_DEVICE_IOCR, iocr);
 224
 225     // Scale timer0 clock
 226     HAL_WRITE_UINT32(CYG_DEVICE_CPM_CT0CCR, CT_X16);
 227
 228     // Initialize counter, mode 2 = rate generator
 229     HAL_WRITE_UINT8(CYG_DEVICE_TIMER_CTL,
 230                     TIMER_CTL_TYPE_BIN|
 231                     TIMER_CTL_MODE_RG|
 232                     TIMER_CTL_RW_BOTH|
 233                     TIMER_CTL_SC_CTR0);
 234     HAL_WRITE_UINT8(CYG_DEVICE_TIMER0, (period & 0xFF));        // LSB
 235     HAL_WRITE_UINT8(CYG_DEVICE_TIMER0, ((period >> 8) & 0xFF)); // MSB
 236     // Enable timer
 237     iocr = (iocr & ~IOCR_CT0G) | IOCR_CT0G_HIGH;
 238     HAL_WRITE_UINT32(CYG_DEVICE_IOCR, iocr);
 239     _period = period;
 240 #ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
 241     cyg_drv_interrupt_create(CYGNUM_HAL_INTERRUPT_EXT0,
 242                              99,           // Priority
 243                              0,            // Data item passed to interrupt handler
 244                              aeb_abort_isr,
 245                              0,
 246                              &abort_interrupt_handle,
 247                              &abort_interrupt);
 248     cyg_drv_interrupt_attach(abort_interrupt_handle);
 249     cyg_drv_interrupt_unmask(CYGNUM_HAL_INTERRUPT_EXT0);
 250 #endif
 251 #ifdef _TIMERS_TESTING
 252     aeb_setup_timer1(period/10);
 253 #endif
 254 }
 255
 256 void hal_clock_reset(cyg_uint32 vector, cyg_uint32 period)
 257 {
 258     _period = period;
 259 }
 260
 261 void hal_clock_read(cyg_uint32 *pvalue)
 262 {
 263     cyg_uint32 value;
 264     cyg_uint8 reg;
 265     do {
 266         HAL_WRITE_UINT8(CYG_DEVICE_TIMER_CTL,
 267                         TIMER_CTL_RW_LATCH|TIMER_CTL_SC_CTR0);
 268         HAL_READ_UINT8(CYG_DEVICE_TIMER0, reg); // LSB
 269         value = reg;
 270         HAL_READ_UINT8(CYG_DEVICE_TIMER0, reg); // MSB
 271         value |= (reg << 8);
 272     } while (value <= 2);  // Hardware malfunction?
 273     *pvalue = _period - (value & 0xFFFF);   // Note: counter is only 16 bits
 274                                             // and decreases
 275 }
 276
 277 void hal_hardware_init(void)
 278 {
 279     // Any hardware/platform initialization that needs to be done.
 280     // Set all unknowns as edge triggered
 281     HAL_WRITE_UINT32(CYG_DEVICE_ICTL_ICR0,
 282                      ICTL_ICR0_CH0_HL_AL|ICTL_ICR0_CH0_EL_ET|
 283                      ICTL_ICR0_CH1_HL_AL|ICTL_ICR0_CH1_EL_ET|
 284                      ICTL_ICR0_CH2_HL_AL|ICTL_ICR0_CH2_EL_ET|
 285                      ICTL_ICR0_CH3_HL_AL|ICTL_ICR0_CH3_EL_ET|
 286                      ICTL_ICR0_CH4_HL_AL|ICTL_ICR0_CH4_EL_ET|
 287                      ICTL_ICR0_CH5_HL_AL|ICTL_ICR0_CH5_EL_ET);
 288     HAL_WRITE_UINT32(CYG_DEVICE_ICTL_ICR1,
 289                      ICTL_ICR1_CH6_HL_AL|
 290                      ICTL_ICR1_CH7_HL_AL|
 291                      ICTL_ICR1_CH8_HL_AL);
 292     HAL_WRITE_UINT32(CYG_DEVICE_ICTL_ICLR, 0xFFFF);  // CLear all interrupts
 293     HAL_WRITE_UINT32(CYG_DEVICE_ICTL_IRQER, 0x0000);  // All disabled
 294     // Clear and initialize cache
 295     HAL_UCACHE_INVALIDATE_ALL();
 296     HAL_UCACHE_ENABLE();
 297
 298     // Set up eCos/ROM interfaces
 299     hal_if_init();
 300 }
 301
 302 //
 303 // This routine is called to respond to a hardware interrupt (IRQ).  It
 304 // should interrogate the hardware and return the IRQ vector number.
 305
 306 int hal_IRQ_handler(void)
 307 {
 308     // Do hardware-level IRQ handling
 309     int irq_status, vector;
 310     HAL_READ_UINT32(CYG_DEVICE_ICTL_IRQSR, irq_status);
 311     for (vector = 0;  vector < 16;  vector++) {
 312         if (irq_status & (1<<vector)) return vector;
 313     }
 314     return CYGNUM_HAL_INTERRUPT_NONE; // This shouldn't happen!
 315 }
 316
 317 //
 318 // Interrupt control
 319 //
 320
 321 void hal_interrupt_mask(int vector)
 322 {
 323     cyg_uint32 mask, old_mask;
 324     HAL_READ_UINT32(CYG_DEVICE_ICTL_IRQER, mask);
 325     old_mask = mask;
 326     mask &= ~(1<<vector);
 327     HAL_WRITE_UINT32(CYG_DEVICE_ICTL_IRQER, mask);
 328 }
 329
 330 #if 0
 331 void hal_interrupt_status(void)
 332 {
 333     int irq_status, irq_enable, ipr_value, timer_value;
 334     cyg_uint8 reg;
 335     HAL_READ_UINT8(CYG_DEVICE_TIMER0, reg); // LSB
 336     timer_value = reg;
 337     HAL_READ_UINT8(CYG_DEVICE_TIMER0, reg); // MSB
 338     timer_value |= (reg << 8);
 339     HAL_READ_UINT32(CYG_DEVICE_ICTL_IRQSR, irq_status);
 340     HAL_READ_UINT32(CYG_DEVICE_ICTL_IRQER, irq_enable);
 341     HAL_READ_UINT32(CYG_DEVICE_ICTL_IPR, ipr_value);
 342     diag_printf("Interrupt: IRQ: %x.%x.%x, Timer: %x\n", irq_status,
 343                 irq_enable, ipr_value, timer_value);
 344 }
 345 #endif
 346
 347 void hal_interrupt_unmask(int vector)
 348 {
 349     cyg_uint32 mask, old_mask;
 350     HAL_READ_UINT32(CYG_DEVICE_ICTL_IRQER, mask);
 351     old_mask = mask;
 352     mask |= (1<<vector);
 353     HAL_WRITE_UINT32(CYG_DEVICE_ICTL_IRQER, mask);
 354 }
 355
 356 void hal_interrupt_acknowledge(int vector)
 357 {
 358     HAL_WRITE_UINT32(CYG_DEVICE_ICTL_ICLR, (1<<vector));
 359 }
 360
 361 void hal_interrupt_configure(int vector, int level, int up)
 362 {
 363 //    diag_printf("%s(%d,%d,%d)\n", __PRETTY_FUNCTION__, vector, level, up);
 364 }
 365
 366 void hal_interrupt_set_level(int vector, int level)
 367 {
 368 //    diag_printf("%s(%d,%d)\n", __PRETTY_FUNCTION__, vector, level);
 369 }
 370
 371 void hal_show_IRQ(int vector, int data, int handler)
 372 {
 373     //    diag_printf("IRQ - vector: %x, data: %x, handler: %x\n", vector,
 374     //                  data, handler);
 375 }
 376
 377 #ifdef _TIMERS_TESTING
 378 #include <cyg/hal/drv_api.h>            // HAL ISR support
 379 static cyg_interrupt timer1_interrupt;
 380 static cyg_handle_t  timer1_interrupt_handle;
 381 static cyg_uint32    timer1_count;
 382
 383 // This ISR is called only for the high speed timer under test
 384 static int
 385 aeb_timer1_isr(cyg_vector_t vector, cyg_addrword_t data, HAL_SavedRegisters *regs)
 386 {
 387     cyg_drv_interrupt_acknowledge(CYGNUM_HAL_INTERRUPT_TIMER1);
 388     timer1_count++;
 389     return 0;  // No need to run DSR
 390 }
 391
 392 static void
 393 aeb_setup_timer1(cyg_uint32 period)
 394 {
 395     cyg_uint32 iocr;
 396
 397     // Set counter GATE input low (0) to halt counter while it's being setup
 398     HAL_READ_UINT32(CYG_DEVICE_IOCR, iocr);
 399     iocr = (iocr & ~IOCR_CT1G) | IOCR_CT1G_LOW;
 400     HAL_WRITE_UINT32(CYG_DEVICE_IOCR, iocr);
 401
 402     // Scale timer0 clock
 403     HAL_WRITE_UINT32(CYG_DEVICE_CPM_CT1CCR, CT_X16);
 404
 405     // Initialize counter, mode 2 = rate generator
 406     HAL_WRITE_UINT8(CYG_DEVICE_TIMER_CTL,
 407                     TIMER_CTL_TYPE_BIN|
 408                     TIMER_CTL_MODE_RG|
 409                     TIMER_CTL_RW_BOTH|
 410                     TIMER_CTL_SC_CTR1);
 411     HAL_WRITE_UINT8(CYG_DEVICE_TIMER1, (period & 0xFF));        // LSB
 412     HAL_WRITE_UINT8(CYG_DEVICE_TIMER1, ((period >> 8) & 0xFF)); // MSB
 413     // Enable timer
 414     iocr = (iocr & ~IOCR_CT1G) | IOCR_CT1G_HIGH;
 415     HAL_WRITE_UINT32(CYG_DEVICE_IOCR, iocr);
 416     cyg_drv_interrupt_create(CYGNUM_HAL_INTERRUPT_TIMER1,
 417                              99,             // Priority
 418                              0,              // Data item passed to interrupt handler
 419                              aeb_timer1_isr,
 420                              0,
 421                              &timer1_interrupt_handle,
 422                              &timer1_interrupt);
 423     cyg_drv_interrupt_attach(timer1_interrupt_handle);
 424     cyg_drv_interrupt_unmask(CYGNUM_HAL_INTERRUPT_TIMER1);
 425 }
 426 #endif
 427
 428 //-----------------------------------------------------------------------------
 429 // Reset board (definitions from watchdog file aeb1.cxx)
 430
 431 // Register definitions
 432 #define CYGARC_REG_WATCHDOG_BASE        0xFFFFAC00
 433 #define CYGARC_REG_WATCHDOG_WDCTLR      (CYGARC_REG_WATCHDOG_BASE+0x30)
 434 #define CYGARC_REG_WATCHDOG_WDCNTR      (CYGARC_REG_WATCHDOG_BASE+0x34)
 435
 436 // Control register bits
 437 #define CYGARC_REG_WATCHDOG_WDCTLR_EN        0x01 // enable
 438 #define CYGARC_REG_WATCHDOG_WDCTLR_RSP_NMF   0x00 // non-maskable fiq
 439 #define CYGARC_REG_WATCHDOG_WDCTLR_RSP_ER    0x04 // external reset
 440 #define CYGARC_REG_WATCHDOG_WDCTLR_RSP_SR    0x06 // system reset
 441 #define CYGARC_REG_WATCHDOG_WDCTLR_FRZ       0x08 // lock enable bit
 442 #define CYGARC_REG_WATCHDOG_WDCTLR_TOP_MASK  0x70 // time out period
 443
 444 #define CYGARC_REG_WATCHDOG_WDCTLR_TOP_17    0x00 // 2^17
 445 #define CYGARC_REG_WATCHDOG_WDCTLR_TOP_17_P  5242880 // = 5.2ms
 446
 447 #define CYGARC_REG_WATCHDOG_WDCTLR_TOP_25    0x40 // 2^25
 448 #define CYGARC_REG_WATCHDOG_WDCTLR_TOP_25_P  1342177300 // = 1.3421773s
 449
 450 void
 451 hal_aeb_reset(void)
 452 {
 453     // Clear the watchdog counter.
 454     HAL_WRITE_UINT32(CYGARC_REG_WATCHDOG_WDCNTR, 0);
 455
 456     // Enable the watchdog with the smallest timeout.
 457     HAL_WRITE_UINT8(CYGARC_REG_WATCHDOG_WDCTLR,
 458                     (CYGARC_REG_WATCHDOG_WDCTLR_TOP_17
 459                      | CYGARC_REG_WATCHDOG_WDCTLR_FRZ
 460                      | CYGARC_REG_WATCHDOG_WDCTLR_RSP_SR
 461                      | CYGARC_REG_WATCHDOG_WDCTLR_EN));
 462
 463     // Wait for it...
 464     for(;;);
 465 }
 466
 467 /*------------------------------------------------------------------------*/
 468 // EOF hal_misc.c