1 //==========================================================================
5 // HAL misc board support code for ARM9/EXCALIBUR
7 //==========================================================================
8 //####ECOSGPLCOPYRIGHTBEGIN####
9 // -------------------------------------------
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38 // -------------------------------------------
39 //####ECOSGPLCOPYRIGHTEND####
40 //==========================================================================
41 //#####DESCRIPTIONBEGIN####
44 // Contributors: gthomas, jskov
46 // Purpose: HAL board support
47 // Description: Implementations of HAL board interfaces
49 //####DESCRIPTIONEND####
51 //==========================================================================
53 #include <pkgconf/hal.h>
54 #include <pkgconf/system.h>
55 #include CYGBLD_HAL_PLATFORM_H
57 #include <cyg/infra/cyg_type.h> // base types
58 #include <cyg/infra/cyg_trac.h> // tracing macros
59 #include <cyg/infra/cyg_ass.h> // assertion macros
61 #include <cyg/hal/hal_io.h> // IO macros
62 #include <cyg/hal/hal_arch.h> // Register state info
63 #include <cyg/hal/hal_diag.h>
64 #include <cyg/hal/hal_intr.h> // Interrupt names
65 #include <cyg/hal/hal_cache.h>
66 #include <cyg/hal/excalibur.h> // Platform specifics
68 #include <cyg/infra/diag.h> // diag_printf
70 #include <string.h> // memset
72 // -------------------------------------------------------------------------
73 // MMU initialization:
75 // These structures are laid down in memory to define the translation
79 // ARM Translation Table Base Bit Masks
80 #define ARM_TRANSLATION_TABLE_MASK 0xFFFFC000
82 // ARM Domain Access Control Bit Masks
83 #define ARM_ACCESS_TYPE_NO_ACCESS(domain_num) (0x0 << (domain_num)*2)
84 #define ARM_ACCESS_TYPE_CLIENT(domain_num) (0x1 << (domain_num)*2)
85 #define ARM_ACCESS_TYPE_MANAGER(domain_num) (0x3 << (domain_num)*2)
87 struct ARM_MMU_FIRST_LEVEL_FAULT {
91 #define ARM_MMU_FIRST_LEVEL_FAULT_ID 0x0
93 struct ARM_MMU_FIRST_LEVEL_PAGE_TABLE {
98 int base_address : 23;
100 #define ARM_MMU_FIRST_LEVEL_PAGE_TABLE_ID 0x1
102 struct ARM_MMU_FIRST_LEVEL_SECTION {
111 int base_address : 12;
113 #define ARM_MMU_FIRST_LEVEL_SECTION_ID 0x2
115 struct ARM_MMU_FIRST_LEVEL_RESERVED {
119 #define ARM_MMU_FIRST_LEVEL_RESERVED_ID 0x3
121 #define ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, table_index) \
122 (unsigned long *)((unsigned long)(ttb_base) + ((table_index) << 2))
124 #define ARM_FIRST_LEVEL_PAGE_TABLE_SIZE 0x4000
126 #define ARM_MMU_SECTION(ttb_base, actual_base, virtual_base, \
127 cacheable, bufferable, perm) \
129 register union ARM_MMU_FIRST_LEVEL_DESCRIPTOR desc; \
132 desc.section.id = ARM_MMU_FIRST_LEVEL_SECTION_ID; \
133 desc.section.imp = 1; \
134 desc.section.domain = 0; \
135 desc.section.c = (cacheable); \
136 desc.section.b = (bufferable); \
137 desc.section.ap = (perm); \
138 desc.section.base_address = (actual_base); \
139 *ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, (virtual_base)) \
143 #define X_ARM_MMU_SECTION(abase,vbase,size,cache,buff,access) \
144 { int i; int j = abase; int k = vbase; \
145 for (i = size; i > 0 ; i--,j++,k++) \
147 ARM_MMU_SECTION(ttb_base, j, k, cache, buff, access); \
151 union ARM_MMU_FIRST_LEVEL_DESCRIPTOR {
153 struct ARM_MMU_FIRST_LEVEL_FAULT fault;
154 struct ARM_MMU_FIRST_LEVEL_PAGE_TABLE page_table;
155 struct ARM_MMU_FIRST_LEVEL_SECTION section;
156 struct ARM_MMU_FIRST_LEVEL_RESERVED reserved;
159 #define ARM_UNCACHEABLE 0
160 #define ARM_CACHEABLE 1
161 #define ARM_UNBUFFERABLE 0
162 #define ARM_BUFFERABLE 1
164 #define ARM_ACCESS_PERM_NONE_NONE 0
165 #define ARM_ACCESS_PERM_RO_NONE 0
166 #define ARM_ACCESS_PERM_RO_RO 0
167 #define ARM_ACCESS_PERM_RW_NONE 1
168 #define ARM_ACCESS_PERM_RW_RO 2
169 #define ARM_ACCESS_PERM_RW_RW 3
174 unsigned long ttb_base = EXCALIBUR_SDRAM_PHYS_BASE + 0x4000;
177 // Set the TTB register
178 asm volatile ("mcr p15,0,%0,c2,c0,0" : : "r"(ttb_base) /*:*/);
180 // Set the Domain Access Control Register
181 i = ARM_ACCESS_TYPE_MANAGER(0) |
182 ARM_ACCESS_TYPE_NO_ACCESS(1) |
183 ARM_ACCESS_TYPE_NO_ACCESS(2) |
184 ARM_ACCESS_TYPE_NO_ACCESS(3) |
185 ARM_ACCESS_TYPE_NO_ACCESS(4) |
186 ARM_ACCESS_TYPE_NO_ACCESS(5) |
187 ARM_ACCESS_TYPE_NO_ACCESS(6) |
188 ARM_ACCESS_TYPE_NO_ACCESS(7) |
189 ARM_ACCESS_TYPE_NO_ACCESS(8) |
190 ARM_ACCESS_TYPE_NO_ACCESS(9) |
191 ARM_ACCESS_TYPE_NO_ACCESS(10) |
192 ARM_ACCESS_TYPE_NO_ACCESS(11) |
193 ARM_ACCESS_TYPE_NO_ACCESS(12) |
194 ARM_ACCESS_TYPE_NO_ACCESS(13) |
195 ARM_ACCESS_TYPE_NO_ACCESS(14) |
196 ARM_ACCESS_TYPE_NO_ACCESS(15);
197 asm volatile ("mcr p15,0,%0,c3,c0,0" : : "r"(i) /*:*/);
199 // First clear all TT entries - ie Set them to Faulting
200 memset((void *)ttb_base, 0, ARM_FIRST_LEVEL_PAGE_TABLE_SIZE);
202 // Memory layout. This is set up in hal_platform_setup.h with
203 // definitions from excalibur.h
205 // SDRAM0_BASE_ADDRESS: 0x00000000, 64M
206 // SDRAM1_BASE_ADDRESS: 0x04000000, 64M
207 // SPSRAM0_BASE_ADDRESS: 0x08000000, 128k
208 // SPSRAM1_BASE_ADDRESS: 0x08020000, 128k
209 // DPSRAM0_BASE_ADDRESS: 0x08040000, 64k
210 // DPSRAM1_BASE_ADDRESS: 0x08050000, 64k
211 // PLD1_BASE_ADDRESS: 0x0f000000, 16k
212 // EBI0_BASE_ADDRESS: 0x40000000, 16M
213 // REGISTERS_BASE_ADDRESS: 0x7fffc000, 16k
214 // PLD0_BASE_ADDRESS: 0x80000000, 128k
216 // Actual Virtual Size Attributes Function
217 // Base Base MB cached? buffered? access permissions
219 X_ARM_MMU_SECTION(0x000, 0x000, 128, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); // SDRAM (& LCD registers?)
220 X_ARM_MMU_SECTION(0x080, 0x080, 1, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); // SRAM regions
221 X_ARM_MMU_SECTION(0x0f0, 0x0f0, 1, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); // PLD1
222 X_ARM_MMU_SECTION(0x400, 0x400, 16, ARM_UNCACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); // Boot flash ROMspace CS0
223 X_ARM_MMU_SECTION(0x800, 0x800, 1, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); // PLD0/2/3
224 X_ARM_MMU_SECTION(0x7ff, 0x7ff, 1, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); // EXCALIBUR registers
227 //----------------------------------------------------------------------------
228 // Platform specific initialization
231 plf_hardware_init(void)
233 // Disable PLD interrupts
234 HAL_WRITE_UINT32(EXCALIBUR_INT_MASK_CLEAR,
235 EXCALIBUR_INT_SOURCE_P0 | EXCALIBUR_INT_SOURCE_P1 |
236 EXCALIBUR_INT_SOURCE_P2 | EXCALIBUR_INT_SOURCE_P3 |
237 EXCALIBUR_INT_SOURCE_P4 | EXCALIBUR_INT_SOURCE_P5);
238 // Make PLD0 generate IRQ
239 HAL_WRITE_UINT32(EXCALIBUR_INT_PRIORITY_0, 0);
242 // -------------------------------------------------------------------------
244 hal_clock_initialize(cyg_uint32 period)
248 HAL_WRITE_UINT32(EXCALIBUR_TIMER0_CR, 0);
249 HAL_WRITE_UINT32(EXCALIBUR_TIMER0_PRE, CYGNUM_HAL_ARM_EXCALIBUR_TIMER_PRESCALE - 1);
250 HAL_WRITE_UINT32(EXCALIBUR_TIMER0_LIMIT, period);
251 cr = EXCALIBUR_TIMER_CR_MODE_HEARBEAT | EXCALIBUR_TIMER_CR_IE;
252 HAL_WRITE_UINT32(EXCALIBUR_TIMER0_CR, cr);
253 HAL_WRITE_UINT32(EXCALIBUR_TIMER0_CR, cr | EXCALIBUR_TIMER_CR_S);
255 // Unmask timer 0 interrupt
256 HAL_INTERRUPT_CONFIGURE( CYGNUM_HAL_INTERRUPT_RTC, 1, 1 );
257 HAL_INTERRUPT_UNMASK( CYGNUM_HAL_INTERRUPT_RTC );
260 // This routine is called during a clock interrupt.
262 hal_clock_reset(cyg_uint32 vector, cyg_uint32 period)
266 // Clear pending interrupt bit
267 HAL_READ_UINT32(EXCALIBUR_TIMER0_CR, cr);
268 cr |= EXCALIBUR_TIMER_CR_CI;
269 HAL_WRITE_UINT32(EXCALIBUR_TIMER0_CR, cr);
272 // Read the current value of the clock, returning the number of hardware
273 // "ticks" that have occurred (i.e. how far away the current value is from
277 hal_clock_read(cyg_uint32 *pvalue)
281 HAL_READ_UINT32(EXCALIBUR_TIMER0_READ, ctr);
286 // Delay for some number of micro-seconds
289 hal_delay_us(cyg_int32 usecs)
293 // Divide by 1000000 in two steps to preserve precision.
294 cyg_uint32 wait_clocks = ((CYGNUM_HAL_ARM_EXCALIBUR_PERIPHERAL_CLOCK/100000)*usecs)/10;
296 HAL_WRITE_UINT32(EXCALIBUR_TIMER1_CR, 0);
297 HAL_WRITE_UINT32(EXCALIBUR_TIMER1_PRE, 0);
298 HAL_WRITE_UINT32(EXCALIBUR_TIMER1_LIMIT, wait_clocks);
299 cr = EXCALIBUR_TIMER_CR_MODE_ONE_SHOT|EXCALIBUR_TIMER_CR_CI;
300 HAL_WRITE_UINT32(EXCALIBUR_TIMER1_CR, cr);
301 HAL_WRITE_UINT32(EXCALIBUR_TIMER1_CR, cr | EXCALIBUR_TIMER_CR_S);
303 // wait for start bit to clear
305 HAL_READ_UINT32(EXCALIBUR_TIMER1_CR, cr);
306 } while ((EXCALIBUR_TIMER_CR_S & cr) != 0);
308 //clear interrupt flag
309 HAL_WRITE_UINT32(EXCALIBUR_TIMER1_CR, 0);
312 // -------------------------------------------------------------------------
314 // This routine is called to respond to a hardware interrupt (IRQ). It
315 // should interrogate the hardware and return the IRQ vector number.
317 hal_IRQ_handler(void)
322 HAL_READ_UINT32(EXCALIBUR_INT_REQUEST_STATUS, isr);
323 for (vec = CYGNUM_HAL_INTERRUPT_PLD_0;
324 vec <= CYGNUM_HAL_INTERRUPT_FAST_COMMS; vec++) {
325 if (isr & (1<<vec)) {
330 return CYGNUM_HAL_INTERRUPT_NONE;
333 //----------------------------------------------------------------------------
337 hal_interrupt_mask(int vector)
339 CYG_ASSERT(vector <= CYGNUM_HAL_ISR_MAX &&
340 vector >= CYGNUM_HAL_ISR_MIN , "Invalid vector");
342 HAL_WRITE_UINT32(EXCALIBUR_INT_MASK_CLEAR, 1<<vector);
346 hal_interrupt_unmask(int vector)
348 CYG_ASSERT(vector <= CYGNUM_HAL_ISR_MAX &&
349 vector >= CYGNUM_HAL_ISR_MIN , "Invalid vector");
351 HAL_WRITE_UINT32(EXCALIBUR_INT_MASK_SET, 1<<vector);
355 hal_interrupt_acknowledge(int vector)
357 CYG_ASSERT(vector <= CYGNUM_HAL_ISR_MAX &&
358 vector >= CYGNUM_HAL_ISR_MIN , "Invalid vector");
363 hal_interrupt_configure(int vector, int level, int up)
365 CYG_ASSERT(vector <= CYGNUM_HAL_ISR_MAX &&
366 vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector");
367 CYG_ASSERT(level || up, "Cannot do falling edge");
372 hal_interrupt_set_level(int vector, int level)
375 CYG_ASSERT(vector <= CYGNUM_HAL_ISR_MAX &&
376 vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector");
377 CYG_ASSERT(level <= 63 && level >= 0, "Invalid level");
379 HAL_READ_UINT32(EXCALIBUR_INT_PRIORITY_0+4*vector, reg);
380 reg &= ~EXCALIBUR_INT_PRIORITY_LVL_mask;
381 reg |= (level & EXCALIBUR_INT_PRIORITY_LVL_mask);
382 HAL_WRITE_UINT32(EXCALIBUR_INT_PRIORITY_0+4*vector, reg);
385 #include CYGHWR_MEMORY_LAYOUT_H
386 typedef void code_fun(void);
387 void excalibur_program_new_stack(void *func)
389 register CYG_ADDRESS stack_ptr asm("sp");
390 register CYG_ADDRESS old_stack asm("r4");
391 register code_fun *new_func asm("r0");
392 old_stack = stack_ptr;
393 stack_ptr = CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE - sizeof(CYG_ADDRESS);
394 new_func = (code_fun*)func;
396 stack_ptr = old_stack;