1 //=============================================================================
5 // HAL diagnostic output code
7 //=============================================================================
8 //####ECOSGPLCOPYRIGHTBEGIN####
9 // -------------------------------------------
10 // This file is part of eCos, the Embedded Configurable Operating System.
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27 // or inline functions from this file, or you compile this file and link it
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38 // -------------------------------------------
39 //####ECOSGPLCOPYRIGHTEND####
40 //=============================================================================
41 //#####DESCRIPTIONBEGIN####
43 // Author(s): Patrick Doyle <wpd@delcomsys.com>
44 // Contributors:Patrick Doyle <wpd@delcomsys.com>
46 // Purpose: HAL diagnostic output
47 // This file contains the type definitions, constants, and function
48 // prototoypes that implement very simple access to the UART on the
50 // Description: Implementations of HAL diagnostic output support.
52 //####DESCRIPTIONEND####
54 //=============================================================================
56 #include <pkgconf/hal.h>
57 #include CYGBLD_HAL_VARIANT_H // Variant specific configuration
58 #include CYGBLD_HAL_PLATFORM_H // Platform specific configuration
60 #include <cyg/infra/cyg_type.h> // base types
61 #include <cyg/infra/cyg_trac.h> // tracing macros
62 #include <cyg/infra/cyg_ass.h> // assertion macros
64 #include <cyg/hal/hal_arch.h> // basic machine info
65 #include <cyg/hal/hal_intr.h> // interrupt macros
66 #include <cyg/hal/hal_io.h> // IO macros
67 #include <cyg/hal/hal_diag.h>
68 #include <cyg/hal/drv_api.h>
69 #include <cyg/hal/hal_if.h> // interface API
70 #include <cyg/hal/hal_misc.h> // Helper functions
71 #include <cyg/hal/innovator.h> // platform definitions
73 //-----------------------------------------------------------------------------
75 #define CYG_DEVICE_SERIAL_BAUD_DIV (CYGNUM_HAL_ARM_INNOVATOR_PERIPHERAL_CLOCK/CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD/16)
76 #define CYG_DEVICE_SERIAL_BAUD_LSB (CYG_DEVICE_SERIAL_BAUD_DIV&0xff)
77 #define CYG_DEVICE_SERIAL_BAUD_MSB ((CYG_DEVICE_SERIAL_BAUD_DIV>>8)&0xff)
79 //-----------------------------------------------------------------------------
81 cyg_int32 msec_timeout;
88 /************************************************************************
89 * Useful definitions -- note that 'USE_MODEM_UART' has not been extensively
90 * tested nor debugged (read -- it probably doesn't work).
91 ************************************************************************/
92 /*#define USE_MODEM_UART*/
94 #define BASE_ADDR 0xfffce800
97 #define BASE_ADDR 0xfffb0000
127 /************************************************************************
128 * Data local to this file
129 ************************************************************************/
130 #define write_serial(offset, value) \
131 *(volatile char *)(BASE_ADDR + STRIDE * (offset)) = value
133 #define read_serial(offset) \
134 (*(volatile char *)(BASE_ADDR + STRIDE * (offset)))
136 /************************************************************************
138 ************************************************************************/
140 /************************************************************************
145 * This procedure may be called in order to initialize the UART
149 * Set up the UART for 115,200 baud, 8 bits, 1 stop bit, no parity.
151 * The UART is defined by the 'BASE_ADDR' macro.
154 * This pays some lip service to being able to use UART3, but since
155 * it seems to me that the use of UART3 requires that the DSP do
156 * some setup (at least, until I learn more), it probably won't
158 ************************************************************************/
160 quick_init_uart(void)
162 /* UART Software Reset */
163 write_serial(LCR, 0xBF); /* Access to EFR & UART break is removed */
164 write_serial(EFR, BIT_04); /* Set EFR[4] = 0x1 */
165 write_serial(LCR, 0x00); /* Access to IER & MCR is allowed */
167 write_serial(IER, 0x00); /* Disable all interrupts */
168 write_serial(MCR, 0x00); /* DTR, RTS, XON, loopbback inactive */
170 write_serial(MDR1,0x07); /* UART is in reset */
172 /* UART FIFO Configuration */
173 write_serial(MCR, read_serial(MCR) | BIT_06); /* Set MCR[6] = 1 */
174 write_serial(TCR, 0x0F); /* RTS off when Rx FIFO at 60 bytes, on at 0 */
175 write_serial(TLR, 0x88); /* set TX & RX trigger levels each to 32 */
176 write_serial(FCR, 0x07); /* Enable & reset FIFOs, triggers at 8 */
177 write_serial(LCR, 0xBF); /* Access EFR */
178 write_serial(EFR, 0xC0); /* Enable auto RTS & CTS */
179 write_serial(LCR, 0x00); /* Access to IER & MCR is allowed */
180 write_serial(MCR, read_serial(MCR) & ~BIT_06); /* Clear MCR[6] */
182 /* Baud Rate and Stop Configuration */
183 write_serial(LCR, 0x03); /* 8,N,1 */
184 #ifdef USE_MODEM_UART
185 write_serial(LCR, 0x83); /* gain access to DLH and DLL */
186 write_serial(DLH, 0x00); /* Divisor value = Operating Freq/(16 x Baud Rate) */
187 write_serial(DLL, 0x0D); /* DPLL2 configured for Operating Freq = 24 MHz */
188 /* Baud Rate = 115,200 bps */
190 write_serial(OSC_12M, 1);/* Set divisor value to 6.5 */
191 write_serial(LCR, 0x83); /* gain access to DLH and DLL */
192 write_serial(DLH, 0x00); /* Divisor value =
193 * Operating Freq/(16 x 6.5 x Baud Rate) */
194 write_serial(DLL, 0x01); /* DPLL2 configured for Operating Freq = 12 MHz */
195 /* Baud Rate = 115,200 bps */
197 write_serial(LCR, 0x03); /* restore LCR */
199 write_serial(MDR1,0x00); /* enable UART */
202 /************************************************************************
207 * This procedure may be called in order to output a character on
208 * the serial port. It blocks until the serial port TX FIFO is
212 * Write character to the Transmit Holding Register (THR). Can
213 * optionally map the Linefeed character to a Carriage Return
214 * character and/or output a Carriage Return character whenever
215 * a Linefeed character is seen, depending on #ifdefs.
218 * This could be optimized to block only when the serial port TX
220 ************************************************************************/
222 quick_putchar(char c)
224 /* #define MAP_LF_TO_CR */
230 while ((read_serial(LSR) & 0x20) == 0) ;
231 write_serial(THR, c);
233 /* #define DO_CRLF */
241 /************************************************************************
246 * This function may be called in order to read a character from
250 * Poll the Line Status register until it indicates a character has
251 * been received. Return the character to the caller.
255 ************************************************************************/
259 while ((read_serial(LSR) & 0x01) == 0) ;
260 return(read_serial(RHR));
263 /************************************************************************
268 * This function may be called in order to read a character from
272 * Poll the Line Status register until it indicates a character has
273 * been received. Return the character to the caller.
277 ************************************************************************/
279 quick_getchar_nonblock(char *c)
281 if ((read_serial(LSR) & 0x01) == 0) {
284 *c = read_serial(RHR);
289 //-----------------------------------------------------------------------------
292 cyg_hal_plf_serial_init_channel(void* __ch_data)
295 cyg_uint32 base = ((channel_data_t*)__ch_data)->base;
298 HAL_WRITE_UINT32(base+_UART_MC, _UART_MC_8BIT | _UART_MC_1STOP | _UART_MC_PARITY_NONE);
300 HAL_WRITE_UINT32(base+_UART_DIV_LO, CYG_DEVICE_SERIAL_BAUD_LSB);
301 HAL_WRITE_UINT32(base+_UART_DIV_HI, CYG_DEVICE_SERIAL_BAUD_MSB);
302 HAL_WRITE_UINT32(base+_UART_FCR, (_UART_FCR_TC | _UART_FCR_RC |
303 _UART_FCR_TX_THR_15 | _UART_FCR_RX_THR_1)); // clear & enableFIFO
305 // enable RX interrupts - otherwise ISR cannot be polled. Actual
306 // interrupt control of serial happens via INT_MASK
307 HAL_WRITE_UINT32(base+_UART_IES, _UART_INTS_RE);
312 cyg_hal_plf_serial_putc(void *__ch_data, char c)
315 cyg_uint32 base = ((channel_data_t*)__ch_data)->base;
317 CYGARC_HAL_SAVE_GP();
320 HAL_READ_UINT32(base+_UART_TSR, tsr);
321 // Wait for TXI flag to be set - or for the register to be
322 // zero (works around a HW bug it seems).
323 } while (tsr && (tsr & _UART_TSR_TXI) == 0);
325 HAL_WRITE_UINT32(base+_UART_TD, (cyg_uint32)(unsigned char)c);
327 CYGARC_HAL_RESTORE_GP();
334 cyg_hal_plf_serial_getc_nonblock(void* __ch_data, cyg_uint8* ch)
337 cyg_uint32 base = ((channel_data_t*)__ch_data)->base;
338 cyg_uint32 rsr, isr, data;
340 HAL_READ_UINT32(base+_UART_ISR, isr);
341 if (0 == (isr & _UART_INTS_RI)) {
342 HAL_READ_UINT32(base+_UART_RSR, rsr);
347 HAL_READ_UINT32(base+_UART_RD, data);
348 *ch = (cyg_uint8)(data & 0xff);
350 // Read RSR to clear interrupt, and RDS to clear errors
351 HAL_READ_UINT32(base+_UART_RSR, data);
352 HAL_READ_UINT32(base+_UART_RDS, data);
356 return(quick_getchar_nonblock(ch));
361 cyg_hal_plf_serial_getc(void* __ch_data)
365 CYGARC_HAL_SAVE_GP();
367 while(!cyg_hal_plf_serial_getc_nonblock(__ch_data, &ch));
369 CYGARC_HAL_RESTORE_GP();
372 return(quick_getchar());
376 static channel_data_t innovator_ser_channels[1] = {
381 cyg_hal_plf_serial_write(void* __ch_data, const cyg_uint8* __buf,
384 CYGARC_HAL_SAVE_GP();
387 cyg_hal_plf_serial_putc(__ch_data, *__buf++);
389 CYGARC_HAL_RESTORE_GP();
393 cyg_hal_plf_serial_read(void* __ch_data, cyg_uint8* __buf, cyg_uint32 __len)
395 CYGARC_HAL_SAVE_GP();
398 *__buf++ = cyg_hal_plf_serial_getc(__ch_data);
400 CYGARC_HAL_RESTORE_GP();
404 cyg_hal_plf_serial_getc_timeout(void* __ch_data, cyg_uint8* ch)
407 channel_data_t* chan = (channel_data_t*)__ch_data;
409 CYGARC_HAL_SAVE_GP();
411 delay_count = chan->msec_timeout * 10; // delay in .1 ms steps
414 res = cyg_hal_plf_serial_getc_nonblock(__ch_data, ch);
415 if (res || 0 == delay_count--)
418 CYGACC_CALL_IF_DELAY_US(100);
421 CYGARC_HAL_RESTORE_GP();
426 cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
428 static int irq_state = 0;
429 channel_data_t* chan = (channel_data_t*)__ch_data;
431 CYGARC_HAL_SAVE_GP();
434 case __COMMCTL_IRQ_ENABLE:
437 // Need to keep it enabled to allow polling using ISR
438 //HAL_WRITE_UINT32(chan->base+_UART_IES, _UART_INTS_RE);
441 HAL_INTERRUPT_UNMASK(chan->isr_vector);
444 case __COMMCTL_IRQ_DISABLE:
448 // Need to keep it enabled to allow polling using ISR
449 // HAL_WRITE_UINT32(chan->base+_UART_IEC, _UART_INTS_RE);
452 HAL_INTERRUPT_MASK(chan->isr_vector);
455 case __COMMCTL_DBG_ISR_VECTOR:
457 ret = chan->isr_vector;
462 case __COMMCTL_SET_TIMEOUT:
466 va_start(ap, __func);
468 ret = chan->msec_timeout;
469 chan->msec_timeout = va_arg(ap, cyg_uint32);
476 CYGARC_HAL_RESTORE_GP();
481 cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc,
482 CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
486 channel_data_t* chan = (channel_data_t*)__ch_data;
487 cyg_uint32 isr, ch, rsr;
489 CYGARC_HAL_SAVE_GP();
491 cyg_drv_interrupt_acknowledge(chan->isr_vector);
494 HAL_READ_UINT32(chan->base+_UART_ISR, isr);
495 HAL_READ_UINT32(chan->base+_UART_RSR, rsr);
497 // Again, check both RI and the RX FIFO count.
498 if ( ((isr & _UART_INTS_RI) != 0 ) || (rsr) ) {
500 HAL_READ_UINT32(chan->base+_UART_RD, ch);
503 if( cyg_hal_is_break( &c , 1 ) )
506 res = CYG_ISR_HANDLED;
509 CYGARC_HAL_RESTORE_GP();
517 cyg_hal_plf_serial_init(void)
519 hal_virtual_comm_table_t* comm;
520 int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
523 // Disable interrupts.
524 HAL_INTERRUPT_MASK(innovator_ser_channels[0].isr_vector);
527 cyg_hal_plf_serial_init_channel(&innovator_ser_channels[0]);
532 // Setup procs in the vector table
535 CYGACC_CALL_IF_SET_CONSOLE_COMM(0);
536 comm = CYGACC_CALL_IF_CONSOLE_PROCS();
537 CYGACC_COMM_IF_CH_DATA_SET(*comm, &innovator_ser_channels[0]);
538 CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
539 CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
540 CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
541 CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
542 CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
543 CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
544 CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
546 // Restore original console
547 CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
552 cyg_hal_plf_comms_init(void)
554 static int initialized = 0;
561 cyg_hal_plf_serial_init();
564 //-----------------------------------------------------------------------------
571 //-----------------------------------------------------------------------------