1 2008-07-12 Andrew Lunn <andrew.lunn@ascom.ch>
3 * src/hal_diag_dcc.{ch}
6 * cdl/hal_arm_at91.cdl: Add support for DCC, ie the Debug
7 Communications Channel, which is part of JTAG core of AT91 and
8 most ARM processors. JTAG devices often make this available via a
9 TCP port which can be accessed via telnet. NOTE: Only output to
10 DCC has been tested via diag_printf. Code exists for input, but it
13 2007-03-05 Andrew Lunn <andrew.lunn@ascom.ch>
15 * include/var_io.h: Fix a few typos pointed out by
18 2007-02-13 John Eigelaar <jeigelaar@mweb.co.za>
20 * include/var_io.h: Fixed up the EMAC definitions to work
21 with the brand new EMAC driver
23 2007-02-01 Andrew Lunn <andrew.lunn@ascom.ch>
25 * include/var_io.h: Added PWM registers.
27 2007-01-25 Andrew Lunn <andrew.lunn@ascom.ch>
29 * include/var_io.h (AT91_PITC_VALUE_MASK): New - mask to access
30 the PITC value which is a 20 bit number.
31 * src/timer_pit.c: Change all hard coded mask for the period,
32 some of which were wrong, to use AT91_PITC_VALUE_MASK.
33 When initializing the PIT, remember to decrement the period first.
34 Bugs found by Jim Seymour.
36 2006-09-08 John Eigelaar <jeigelaar@mweb.co.za>
38 * include/var_io.h: Added definition for SPI MODFDIS bit
40 2006-08-31 Oyvind Harboe <oyvind.harboe@zylin.com>
42 * src/at91_misc.c: Now also resets external circuitry via
45 2006-06-01 John Eigelaar <jeigelaar@mweb.co.za>
47 * include/var_io.h: Added SPI PDC register definitions
49 2006-05-20 John Eigelaar <jeigelaar@mweb.co.za>
51 * include/var_io.h: AT91SAM7X pin definitions
52 * include/hal_platform_int.h: AT91SAM7X interrupts
53 * include/plf_io.h: AT91SAM7X device addresses.
55 2006-05-20 Andrew Lunn <andrew.lunn@ascom.ch>
57 * cdl/hal_arm_at91sam7s.cdl: Rename to AT91SAM7 and add support
58 for AT91SAM7X, based on code from John Eigelaar.
59 * include/var_io.h: add CAN, TWI and ADC registers.
61 2006-05-17 Andrew Lunn <andrew.lunn@ascom.ch>
63 * include/var_io.h: Add macros to manipulate the PIO controllers.
65 2006-05-10 Andrew Lunn <andrew.lunn@ascom.ch>
67 * include/var_io.h: Added the Ethernet MAC registers.
69 2006-04-26 John Eigelaar <jeigelaar@mweb.co.za>
71 * include/var_io.h: Fix typo's in the USB register definitions
72 and add definitions for the S2C controller.
74 2006-03-10 Oliver Munz <munz@speag.ch>
76 * src/timer_pit.c: fix hal_delay_us(). hal_clock_read for
77 initializing the PIT if needed. Change hal_clock_reset() to allow
78 setting of a new period. This is required when the timer is
79 started by hal_delay_us() or hal_clock_read() before
80 hal_clock_initialize().
82 2006-03-23 Andrew Lunn <andrew.lunn@ascom.ch>
84 * src/timer_pit.c (hal_delay_us): Start the PIT if it is not
85 running when hal_delay_us is called. This happens when the kernel
86 is not used. Problem found by Oliver Munz.
88 2006-03-10 Oliver Munz <munz@speag.ch>
90 * src/hal_diag.c (cyg_hal_plf_serial_isr): Change the #ifdefs to
91 cleanly match the CDL.
93 2006-02-28 Andrew Lunn <andrew.lunn@ascom.ch>
94 Oliver Munz <munz@speag.ch>
96 * include/var_io.h (AT91_US_PTCR_RXTDIS): Add bit fields for the
97 USART DMA control register.
99 2006-02-25 Andrew Lunn <andrew.lunn@ascom.ch>
101 * include/var_io.h: Added the USB device registers.
103 2006-02-19 Andrew Lunn <andrew.lunn@ascom.ch>
104 Oliver Munz <munz@speag.ch>
106 * cdl/hal_arm_at9a.cdl: Add the AT91SAM7S variant and control
107 for new timer and debug usart code.
108 * include/var_io.h: Register definitions for AT91SAM7S
109 * include/var_arch.h: Idle action for AT91SAM7S
110 * src/at91_misc.c (hal_hardware_init): Call HAL_PLF_HARDWARE_INIT
111 for any platform specific initialization
112 * src/at91_misc.c (hal_at91_reset_cpu): Use the reset controller
114 * src/at91_misc.c (hal_IRQ_handler): Decode interrupts from
115 the system controller if it exists.
116 * src/timer_tc.c (NEW) eCos timer using the Timer Counter
117 * src/timer_pit.c (NEW) eCos timer using Periodic Interval Timer
118 * src/hal_diag_dbg.c (NEW) Debug output via debug UART.
119 * src/hal_diag.h: Indicate hal_at91_reset_cpu() is a C function
120 otherwise we have problems with the watchdog driver which is C++.
122 2005-05-30 Ezequiel Conde <ezeq@cc.isel.ipl.pt>
124 * src/at91_misc.c ( hal_delay_us ): Clear status before running
127 2004-11-12 Jani Monoses <jani@iv.ro>
129 * include/var_io.h: Added defines for some missing UART bits,
130 corrected a few timer capture mode register bits.
132 2004-11-12 Andrew Lunn <andrew.lunn@ascom.ch>
134 * src/hal_diag.c: Only support the third serial port if we have
135 the defines needed. Not all HAL do have.
137 2004-11-11 Sebastian Block <SebastianBlock@gmx.net>
139 * src/hal_diag.c: Added support for the third serial port
141 2004-10-06 Andrea Michelotti <amichelotti@atmel.com>
143 * include/var_io.h: protected PDC/SPI DMA registers from redefinition.
144 The HAL may of already defined them.
146 2004-10-05 Savin Zlobec <savin@elatec.si>
148 * include/var_io.h: Added definitions for AT91M55800A SPI and PIO
151 2004-09-17 Andrea Michelotti <amichelotti@atmel.com>
153 * cdl/hal_arm_at91.cdl:
156 * include/var_arch.h: added jtst target
158 2004-09-16 Andrea Michelotti <amichelotti@atmel.com>
160 * cdl/hal_arm_at91.cdl:
162 * include/var_io.h: Support FIQ as a high priority interrupt using
163 the normal mechanism. This is controlled by the CDL option
164 CYGHWR_HAL_ARM_AT91_FIQ and uses the interrupt number
165 CYGHWR_HAL_ARM_AT91_FIQ which is common to all platforms using
168 2004-08-30 Thomas Koeller <thomas.koeller@baslerweb.com>
170 * cdl/hal_arm_at91.cdl: Reversed change of 2004-02-12 that move
171 seemingly 'common' options from the platform to the variant. This
172 was breaking some platform HALs.
174 2004-08-12 Jani Monoses <jani@iv.ro>
176 * src/at91_misc.c: Mask all interrupts before calling
177 hal_if_init() not after, so if it creates interrupts
178 they do not get disabled.
180 2004-05-24 Gratian Crisan <nelu@iv.ro>
182 * include/var_io.h: Added waveform mode definitions for
185 2004-02-19 Daniel Néri <daniel.neri@sigicom.se>
187 * cdl/hal_arm_at91.cdl (CYGBLD_GLOBAL_CFLAGS): Honour CYGHWR_THUMB
188 and CYGBLD_ARM_ENABLE_THUMB_INTERWORK.
189 * cdl/hal_arm_at91.cdl (CYGBLD_GLOBAL_LDFLAGS): Ditto.
191 2004-02-18 Daniel Néri <daniel.neri@sigicom.se>
193 * cdl/hal_arm_at91.cdl: Define CYGNUM_HAL_ARM_AT91_CLOCK_SPEED with
194 a default_value so it can be overridden in the platform HAL.
195 * src/hal_diag.c (cyg_hal_plf_serial_control): Properly terminate
196 variable argument processing.
197 * include/hal_diag.h: prototype for hal_at91_set_leds() to avoid
200 2004-02-12 Jani Monoses <jani@iv.ro>
202 * cdl/hal_arm_at91.cdl: Put configuration options common to all
203 variants here. Replace
204 CYGNUM_HAL_VIRTUAL_VECTOR_CHANNELS_DEFAULT_BAUD with the two
205 separate options for console and debug channels as used by most
207 * src/hal_diag.c: Implement
208 CYGINT_HAL_VIRTUAL_VECTOR_COMM_BAUD_SUPPORT so baudrate is
209 changeable from RedBoot.
211 2003-12-05 Andrew Lunn <andrew.lunn@ascom.ch>
213 * include/hal_diag.h: hal_delay_us() is a C function.
215 2003-12-02 Thomas Koeller <thomas.koeller@baslerweb.com>
217 * include/var_io.h: Improved accuracy for baud rate divider
220 2003-10-23 Thomas Koeller <thomas.koeller@baslerweb.com>
222 * src/at91_misc.c: Fixed recognition of spurious
225 2003-08-21 Thomas Koeller <thomas.koeller@baslerweb.com>
230 2003-08-20 Daniel Néri <daniel.neri@sigicom.se>
232 * include/var_io.h: Fix typos (duplicates) from last change.
234 2003-08-18 Thomas Koeller <thomas.koeller@baslerweb.com>
237 Added bitmask definitions for PIO.
239 2003-08-06 Daniel Néri <daniel.neri@sigicom.se>
241 * src/at91_misc.c (hal_clock_reset):
242 Don't acknowledge interrupt here (this is handled
243 in Cyg_RealTimeClock::isr).
245 2003-07-18 Nick Garnett <nickg@balti.calivar.com>
247 * cdl/hal_arm_at91.cdl:
248 Changed values for CYGNUM_HAL_RTC_NUMERATOR,
249 CYGNUM_HAL_RTC_DENOMINATOR and CYGNUM_HAL_RTC_PERIOD to
250 "default_value" from "calculated". This makes it easier
251 to change these values globally.
253 2003-06-25 Daniel Néri <daniel.neri@sigicom.se>
255 * src/at91_misc.c (hal_interrupt_set_level): Fix assert condition;
256 AT91 interrupt priority levels are between 0 and 7.
258 2003-06-24 Jonathan Larmour <jifl@eCosCentric.com>
260 * include/var_io.h: Remove not seemingly useful AT91_PMC_SCER_CPU.
262 * cdl/hal_arm_at91.cdl: We have a var_arch.h so define
263 CYGBLD_HAL_ARM_VAR_ARCH_H.
265 * include/var_arch.h: New file containing
266 overrides for hal_arch.h.
267 (HAL_IDLE_THREAD_ACTION): override here by defining power saving modes
270 2003-06-04 Daniel Néri <daniel.neri@sigicom.se>
272 * src/at91_misc.c (hal_hardware_init): Make sure the AIC internal
273 priority level stack is flushed.
274 (hal_IRQ_handler): Calculate active interrupt by dummy read from
275 the IVR, which has the side-effect of updating ISR with the
276 current interrupt source number.
277 (hal_interrupt_acknowledge): Write to ICCR is not needed, as
278 interrupt deassertion is taken care of by read of IVR in
281 2003-05-27 Daniel Néri <daniel.neri@sigicom.se>
283 * include/var_io.h: Add missing USART register defines.
284 Fix cut'n'paste typos in AT91_PS defines.
286 2003-05-16 Daniel Néri <daniel.neri@sigicom.se>
288 * include/var_io.h: Add missing PIO register defines. Add
289 CPU clock disable command bit.
291 2003-05-15 Thomas Koeller <thomas.koeller@baslerweb.com>
293 * include/hal_diag.h:
294 * src/at91_misc.c: Added function to generate a hardware reset
297 2003-05-15 Nick Garnett <nickg@balti.calivar.com>
299 * src/at91_misc.c (hal_delay_us): Added calculation to better
300 approximate the number of timer ticks for a given number of
301 microseconds. This code also now adjust to the actual CPU clock
302 speed on different platforms.
304 2003-05-12 Nick Garnett <nickg@balti.calivar.com>
306 * src/at91_misc.c: Change definition of hal_IRQ_handler() to be
307 variant-indepenendent, and to use HAL_LSBIT_INDEX() rather than an
308 explicit scan of the ipr bits. Tidied up file a little to make
311 * include/var_io.h: Reorganized to allow platform HALs to define
312 base addresses of on-chip devices if they differ from the defaults
313 defined here. Added variant definitions of Power Management
314 devices for different parts.
316 * cdl/hal_arm_at91.cdl: Calculate CYGNUM_HAL_RTC_PERIOD from
317 CYGNUM_HAL_ARM_AT91_CLOCK_SPEED, which is defined by the platform.
318 Added CYGHWR_HAL_ARM_AT91 to define the specific Atmel AT91 part
319 being supported. This must be defined by the platform HAL.
320 Added define_proc to generate CYGBLD_HAL_ARM_VAR_IO_H.
322 * src/hal_diag.c (hal_diag_led): Now calls hal_at91_set_leds().
324 2002-07-14 Tim Drury <tdrury@siliconmotorsports.com>
326 * cdl/hal_arm_at91.cdl: moved clock speed parameter to platform specific cdl
327 * include/var_io.h: added PIO_PDSR register
328 * src/hal_diag.c: added hal_diag_led()
330 2002-05-28 Thomas Koeller <Thomas.Koeller@baslerweb.com>
332 * include/plf_io.h: Add watchdog definitions.
334 2002-05-08 Gary Thomas <gthomas@redhat.com>
336 * misc/redboot_ROMRAM.ecm:
337 * misc/redboot_ROM.ecm: Disable 'fconfig' since the FLASH is too small.
339 2001-08-17 George Hampton <george.hampton@intel.com>
340 2001-08-17 Gary Thomas <gthomas@redhat.com>
342 * include/hal_platform_ints.h (CYGNUM_HAL_ISR_COUNT): PR 22864
343 Don't adjust by "min" value if not doing translations.
345 2001-07-26 Gary Thomas <gthomas@redhat.com>
347 * src/at91_misc.c (hal_clock_initialize):
348 * cdl/hal_arm_at91.cdl: Increase system clock (RTC) to run at 1MHz for
349 better timing resolution. CAUTION! this means that the system clock tick
350 can never be more than 64ms.
352 2001-07-23 Gary Thomas <gthomas@redhat.com>
354 * include/pkgconf/mlt_arm_at91_eb40_romram.mlt:
355 * include/pkgconf/mlt_arm_at91_eb40_romram.ldi:
356 * include/pkgconf/mlt_arm_at91_eb40_romram.h:
357 * include/pkgconf/mlt_arm_at91_eb40_ram.mlt:
358 * include/pkgconf/mlt_arm_at91_eb40_ram.ldi:
359 * include/pkgconf/mlt_arm_at91_eb40_ram.h:
360 * cdl/hal_arm_at91.cdl: Fix MLT files (names, layout).
362 2001-07-20 Gary Thomas <gthomas@redhat.com>
364 * include/plf_io.h: Add UART interrupt definitions.
366 * src/hal_diag.c (cyg_hal_plf_serial_control): Enable ^C support.
368 * src/at91_misc.c (hal_clock_initialize): Add clock/rtc implementation.
370 * include/pkgconf/mlt_arm_at91_eb40_romram.ldi:
371 Replace missing 'fixed vectors'.
373 2001-07-19 Gary Thomas <gthomas@redhat.com>
375 * misc/redboot_ROMRAM.ecm: New exported config.
377 * include/pkgconf/mlt_arm_at91_eb40_romram.ldi:
378 * include/pkgconf/mlt_arm_at91_eb40_ram.mlt:
379 * include/pkgconf/mlt_arm_at91_eb40_ram.ldi:
380 * include/hal_platform_setup.h: Fix ROMRAM startup mode. Note: I
381 can't get the onboard SRAM at 0x00100000 to work, so for now, this
382 will just have to go in low external RAM. Thus the change for the
383 RAM base address in startup=RAM mode.
385 * src/hal_diag.c (cyg_hal_plf_serial_getc_timeout): Remove debug code.
387 * src/at91_misc.c (set_leds): LEDs are on D4/D2/D1.
389 * misc/redboot_ROM.ecm:
390 * misc/redboot_RAM.ecm: Exported configurations.
392 * include/pkgconf/mlt_arm_at91_eb40_romram.mlt:
393 * include/pkgconf/mlt_arm_at91_eb40_romram.ldi:
394 * include/pkgconf/mlt_arm_at91_eb40_romram.h: New startup type.
396 * include/pkgconf/mlt_arm_at91_eb40_rom.h: Fix heap layout.
398 * include/pkgconf/mlt_arm_at91_eb40_ram.mlt:
399 * include/pkgconf/mlt_arm_at91_eb40_ram.ldi:
400 * include/pkgconf/mlt_arm_at91_eb40_ram.h:
401 Fix heap layout. Move RAM load address to leave room for RedBoot/GDB.
403 * include/plf_io.h: Add definitions for PIO, EBI and PS.
405 * include/hal_platform_setup.h: ROM startup mode now works.
406 First attempt at ROMRAM startup - not yet working.
408 * cdl/hal_arm_at91.cdl: Add ROMRAM startup mode.
410 2001-07-18 Gary Thomas <gthomas@redhat.com>
412 * src/hal_diag.c: More complete initialization.
414 * src/at91_misc.c: Support interrupt controller, delay_us().
416 * include/plf_io.h: Add interrupt controller, timer definitions.
418 * cdl/hal_arm_at91.cdl: Fix clock speed, number I/O channels.
420 2001-07-16 Gary Thomas <gthomas@redhat.com>
424 * include/pkgconf/mlt_arm_at91_eb40_rom.mlt:
425 * include/pkgconf/mlt_arm_at91_eb40_rom.ldi:
426 * include/pkgconf/mlt_arm_at91_eb40_rom.h:
427 * include/pkgconf/mlt_arm_at91_eb40_ram.mlt:
428 * include/pkgconf/mlt_arm_at91_eb40_ram.ldi:
429 * include/pkgconf/mlt_arm_at91_eb40_ram.h:
430 * include/plf_stub.h:
432 * include/hal_platform_setup.h:
433 * include/hal_platform_ints.h:
434 * include/hal_diag.h:
435 * include/hal_cache.h:
436 * cdl/hal_arm_at91.cdl: New port - cloned from E7T.
438 //===========================================================================
439 //####ECOSGPLCOPYRIGHTBEGIN####
440 // -------------------------------------------
441 // This file is part of eCos, the Embedded Configurable Operating System.
442 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
444 // eCos is free software; you can redistribute it and/or modify it under
445 // the terms of the GNU General Public License as published by the Free
446 // Software Foundation; either version 2 or (at your option) any later version.
448 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
449 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
450 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
453 // You should have received a copy of the GNU General Public License along
454 // with eCos; if not, write to the Free Software Foundation, Inc.,
455 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
457 // As a special exception, if other files instantiate templates or use macros
458 // or inline functions from this file, or you compile this file and link it
459 // with other works to produce a work based on this file, this file does not
460 // by itself cause the resulting work to be covered by the GNU General Public
461 // License. However the source code for this file must still be made available
462 // in accordance with section (3) of the GNU General Public License.
464 // This exception does not invalidate any other reasons why a work based on
465 // this file might be covered by the GNU General Public License.
467 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
468 // at http://sources.redhat.com/ecos/ecos-license/
469 // -------------------------------------------
470 //####ECOSGPLCOPYRIGHTEND####
471 //===========================================================================