1 /*=============================================================================
5 // HAL diagnostic output code
7 //=============================================================================
8 //####ECOSGPLCOPYRIGHTBEGIN####
9 // -------------------------------------------
10 // This file is part of eCos, the Embedded Configurable Operating System.
11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
13 // eCos is free software; you can redistribute it and/or modify it under
14 // the terms of the GNU General Public License as published by the Free
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17 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
18 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
19 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
22 // You should have received a copy of the GNU General Public License along
23 // with eCos; if not, write to the Free Software Foundation, Inc.,
24 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
26 // As a special exception, if other files instantiate templates or use macros
27 // or inline functions from this file, or you compile this file and link it
28 // with other works to produce a work based on this file, this file does not
29 // by itself cause the resulting work to be covered by the GNU General Public
30 // License. However the source code for this file must still be made available
31 // in accordance with section (3) of the GNU General Public License.
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34 // this file might be covered by the GNU General Public License.
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37 // at http://sources.redhat.com/ecos/ecos-license/
38 // -------------------------------------------
39 //####ECOSGPLCOPYRIGHTEND####
40 //=============================================================================
41 //#####DESCRIPTIONBEGIN####
44 // Contributors:jskov, gthomas
46 // Purpose: HAL diagnostic output
47 // Description: Implementations of HAL diagnostic output support.
49 //####DESCRIPTIONEND####
51 //===========================================================================*/
53 #include <pkgconf/hal.h>
54 #include CYGBLD_HAL_PLATFORM_H
56 #include <cyg/infra/cyg_type.h> // base types
58 #include <cyg/hal/hal_arch.h> // SAVE/RESTORE GP macros
59 #include <cyg/hal/hal_io.h> // IO macros
60 #include <cyg/hal/hal_if.h> // interface API
61 #include <cyg/hal/hal_intr.h> // HAL_ENABLE/MASK/UNMASK_INTERRUPTS
62 #include <cyg/hal/hal_misc.h> // Helper functions
63 #include <cyg/hal/drv_api.h> // CYG_ISR_HANDLED
64 #include <cyg/hal/hal_diag.h>
66 #include <cyg/hal/var_io.h> // USART registers
68 #include "hal_diag_dcc.h" // DCC initialization file
69 //-----------------------------------------------------------------------------
72 cyg_int32 msec_timeout;
77 //-----------------------------------------------------------------------------
80 cyg_hal_plf_serial_putc(void *__ch_data, char c);
83 cyg_hal_plf_serial_init_channel(void* __ch_data)
85 channel_data_t* chan = (channel_data_t*)__ch_data;
86 cyg_uint8* base = chan->base;
89 HAL_WRITE_UINT32(base+AT91_US_CR, AT91_US_CR_RxRESET | AT91_US_CR_TxRESET);
92 HAL_WRITE_UINT32(base+AT91_US_MR,
93 AT91_US_MR_CLOCK_MCK | AT91_US_MR_LENGTH_8 |
94 AT91_US_MR_PARITY_NONE | AT91_US_MR_STOP_1);
96 HAL_WRITE_UINT32(base+AT91_US_BRG, AT91_US_BAUD(chan->baud_rate));
99 HAL_WRITE_UINT32(base+AT91_US_CR, AT91_US_CR_RxENAB | AT91_US_CR_TxENAB);
104 cyg_hal_plf_serial_putc(void *__ch_data, char c)
106 cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
107 cyg_uint32 status, ch;
108 CYGARC_HAL_SAVE_GP();
111 HAL_READ_UINT32(base+AT91_US_CSR, status);
112 } while ((status & AT91_US_CSR_TxRDY) == 0);
115 HAL_WRITE_UINT32(base+AT91_US_THR, ch);
117 CYGARC_HAL_RESTORE_GP();
121 cyg_hal_plf_serial_getc_nonblock(void* __ch_data, cyg_uint8* ch)
123 channel_data_t* chan = (channel_data_t*)__ch_data;
124 cyg_uint8* base = chan->base;
128 HAL_READ_UINT32(base+AT91_US_CSR, stat);
129 if ((stat & AT91_US_CSR_RxRDY) == 0)
132 HAL_READ_UINT32(base+AT91_US_RHR, c);
133 *ch = (cyg_uint8)(c & 0xff);
139 cyg_hal_plf_serial_getc(void* __ch_data)
142 CYGARC_HAL_SAVE_GP();
144 while(!cyg_hal_plf_serial_getc_nonblock(__ch_data, &ch));
146 CYGARC_HAL_RESTORE_GP();
151 cyg_hal_plf_serial_write(void* __ch_data, const cyg_uint8* __buf,
154 CYGARC_HAL_SAVE_GP();
157 cyg_hal_plf_serial_putc(__ch_data, *__buf++);
159 CYGARC_HAL_RESTORE_GP();
163 cyg_hal_plf_serial_read(void* __ch_data, cyg_uint8* __buf, cyg_uint32 __len)
165 CYGARC_HAL_SAVE_GP();
168 *__buf++ = cyg_hal_plf_serial_getc(__ch_data);
170 CYGARC_HAL_RESTORE_GP();
174 cyg_hal_plf_serial_getc_timeout(void* __ch_data, cyg_uint8* ch)
177 channel_data_t* chan = (channel_data_t*)__ch_data;
179 CYGARC_HAL_SAVE_GP();
181 delay_count = chan->msec_timeout * 10; // delay in .1 ms steps
184 res = cyg_hal_plf_serial_getc_nonblock(__ch_data, ch);
185 if (res || 0 == delay_count--)
188 CYGACC_CALL_IF_DELAY_US(100);
191 CYGARC_HAL_RESTORE_GP();
196 cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
198 static int irq_state = 0;
199 channel_data_t* chan = (channel_data_t*)__ch_data;
200 cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
204 CYGARC_HAL_SAVE_GP();
205 va_start(ap, __func);
208 case __COMMCTL_GETBAUD:
209 ret = chan->baud_rate;
211 case __COMMCTL_SETBAUD:
212 chan->baud_rate = va_arg(ap, cyg_int32);
213 // Should we verify this value here?
214 cyg_hal_plf_serial_init_channel(chan);
217 case __COMMCTL_IRQ_ENABLE:
219 HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector);
220 HAL_INTERRUPT_UNMASK(chan->isr_vector);
221 HAL_WRITE_UINT32(base+AT91_US_IER, AT91_US_IER_RxRDY);
223 case __COMMCTL_IRQ_DISABLE:
226 HAL_INTERRUPT_MASK(chan->isr_vector);
227 HAL_WRITE_UINT32(base+AT91_US_IDR, AT91_US_IER_RxRDY);
229 case __COMMCTL_DBG_ISR_VECTOR:
230 ret = chan->isr_vector;
232 case __COMMCTL_SET_TIMEOUT:
233 ret = chan->msec_timeout;
234 chan->msec_timeout = va_arg(ap, cyg_uint32);
240 CYGARC_HAL_RESTORE_GP();
245 cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc,
246 CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
249 channel_data_t* chan = (channel_data_t*)__ch_data;
253 CYGARC_HAL_SAVE_GP();
256 HAL_READ_UINT32(chan->base+AT91_US_CSR, stat);
257 if ( (stat & AT91_US_CSR_RxRDY) != 0 ) {
259 HAL_READ_UINT32(chan->base+AT91_US_RHR, c);
260 ch = (cyg_uint8)(c & 0xff);
261 if( cyg_hal_is_break( &ch , 1 ) )
264 res = CYG_ISR_HANDLED;
267 HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector);
269 CYGARC_HAL_RESTORE_GP();
273 static channel_data_t at91_ser_channels[CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS] = {
274 #if CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS > 0
275 { (cyg_uint8*)AT91_USART0, 1000, CYGNUM_HAL_INTERRUPT_USART0, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD},
276 #if CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS > 1
277 { (cyg_uint8*)AT91_USART1, 1000, CYGNUM_HAL_INTERRUPT_USART1, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD},
278 #if CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS > 2
279 { (cyg_uint8*)AT91_USART2, 1000, CYGNUM_HAL_INTERRUPT_USART2, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD}
286 cyg_hal_plf_serial_init(void)
288 hal_virtual_comm_table_t* comm;
291 cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
294 #if CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS > 0
295 cyg_hal_plf_serial_init_channel(&at91_ser_channels[0]);
296 #if CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS > 1
297 cyg_hal_plf_serial_init_channel(&at91_ser_channels[1]);
298 #if CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS > 2
299 cyg_hal_plf_serial_init_channel(&at91_ser_channels[2]);
303 // Setup procs in the vector table
306 #if CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS > 0
307 CYGACC_CALL_IF_SET_CONSOLE_COMM(0);
308 comm = CYGACC_CALL_IF_CONSOLE_PROCS();
309 CYGACC_COMM_IF_CH_DATA_SET(*comm, &at91_ser_channels[0]);
310 CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
311 CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
312 CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
313 CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
314 CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
315 CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
316 CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
318 #if CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS > 1
320 CYGACC_CALL_IF_SET_CONSOLE_COMM(1);
321 comm = CYGACC_CALL_IF_CONSOLE_PROCS();
322 CYGACC_COMM_IF_CH_DATA_SET(*comm, &at91_ser_channels[1]);
323 CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
324 CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
325 CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
326 CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
327 CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
328 CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
329 CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
331 #if CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS > 2
332 CYGACC_CALL_IF_SET_CONSOLE_COMM(2);
333 comm = CYGACC_CALL_IF_CONSOLE_PROCS();
334 CYGACC_COMM_IF_CH_DATA_SET(*comm, &at91_ser_channels[2]);
335 CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
336 CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
337 CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
338 CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
339 CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
340 CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
341 CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
346 // Restore original console
347 CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
351 cyg_hal_plf_comms_init(void)
353 static int initialized = 0;
360 cyg_hal_plf_serial_init();
362 #ifdef CYGBLD_HAL_ARM_AT91_DCC
363 cyg_hal_plf_dcc_init(CYGBLD_HAL_ARM_AT91_DCC_CHANNEL);
368 hal_diag_led(int mask)
370 hal_at91_set_leds(mask);
373 //-----------------------------------------------------------------------------