1 //==========================================================================
5 // SDRAM function test 0
7 //==========================================================================
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40 //==========================================================================
41 //#####DESCRIPTIONBEGIN####
46 // Description: Basic memory test, knowledgeable of the EBSA285's
48 //####DESCRIPTIONEND####
50 #include <cyg/infra/testcase.h>
52 #include <cyg/infra/diag.h>
54 #include <cyg/hal/hal_arch.h>
55 #include <cyg/hal/hal_intr.h>
57 #define ONE_MEG (0x100000)
58 #define ONE_MEG_IN_WORDS (ONE_MEG/4)
61 #define WORDS ONE_MEG_IN_WORDS
62 #define START 0x400000
68 #if WORDS > ONE_MEG_IN_WORDS
69 # error "Too many WORDS in a block - they'll overlap!"
72 #include <cyg/hal/hal_ebsa285.h>
76 check_addrsize_setup( void )
78 cyg_uint32 sizes[4] = { 0, };
79 cyg_uint32 bases[4] = { 0, };
80 cyg_uint32 codes[4] = { 0, };
81 cyg_uint32 muxes[4] = { 0, };
86 static cyg_uint32 lookup[] =
87 { 0, 1 MBytes, 2 MBytes, 4 MBytes, 8 MBytes, 16 MBytes, 32 MBytes, 64 MBytes };
89 static cyg_uint32 maxsizes[] =
90 { 2 MBytes, 16 MBytes, 64 MBytes, 8 MBytes, 64 MBytes, 0, 0, 0 };
92 codes[0] = *SA110_SDRAM_ADDRESS_SIZE_ARRAY_0;
93 codes[1] = *SA110_SDRAM_ADDRESS_SIZE_ARRAY_1;
94 codes[2] = *SA110_SDRAM_ADDRESS_SIZE_ARRAY_2;
95 codes[3] = *SA110_SDRAM_ADDRESS_SIZE_ARRAY_3;
97 // Print all the info for the benefit of humans:
98 for ( i = 0; i < 4; i++ ) {
99 bases[i] = 0x0ff00000 & codes[i];
100 sizes[i] = lookup[ 7 & codes[i] ];
101 muxes[i] = 7 & (codes[i] >> 4);
102 diag_printf( "Bank %d: [%08x]: base %08x, size %08x; mux mode %d\n",
103 i, codes[i], bases[i] , sizes[i] , muxes[i] );
105 // THEN check individual entries for sanity
106 for ( i = 0; i < 4; i++ ) {
107 if ( 0 == sizes[i] ) {
108 // then the bank is not in use
109 CYG_TEST_CHECK( 0 == bases[i], "Unused bank nonzero address" );
110 CYG_TEST_CHECK( 0 == muxes[i], "Unused bank nonzero mux mode" );
112 CYG_TEST_CHECK( muxes[i] <= 4, "Mux mode overflow" );
113 if ( (muxes[i] == 3) && (8 != sizes[i]) )
114 CYG_TEST_FAIL( "Mux mode 3 and size not 8Mb" );
115 CYG_TEST_CHECK( maxsizes[ muxes[i] ] >= sizes[i],
116 "Size too larget for mux mode" );
120 // NEXT check that addresses are singly mapped IYSWIM:
121 // Easiest way is, foreach megabyte, check it is mapped exactly once;
122 // shouldn't take too long.
123 for ( i = 0; i < hal_dram_size; i += ONE_MEG ) {
126 for ( k = 0; k < 4; k++ )
127 // this test works OK for an unused slot because i is +ve:
128 if ( (bases[k] <= i) && (i < (bases[k] + sizes[k])) )
130 CYG_TEST_CHECK( 2 > j, "Good memory is multiply mapped" );
131 CYG_TEST_CHECK( 0 < j, "Good memory is not mapped" );
133 for ( /* i */ ; i < 256 MBytes; i += ONE_MEG ) {
136 for ( k = 0; k < 4; k++ )
137 // this test works OK for an unused slot because i is +ve:
138 if ( (bases[k] <= i) && (i < (bases[k] + sizes[k])) )
140 CYG_TEST_CHECK( 2 > j, "Non-existent memory is multiply mapped" );
141 CYG_TEST_CHECK( 0 == j, "Non-existent memory is mapped" );
143 CYG_TEST_PASS( "Memory controller setup self-consistent" );
149 cyg_uint32 h, i, j, k;
150 cyg_uint32 *pbase[ MEGS ] = { 0, };
152 int ptotalerrors[ MEGS ] = { 0, };
157 check_addrsize_setup();
160 h = hal_dram_size - ONE_MEG;
164 while ( (i > k) && (h > j) ) {
165 pbase[i] = (cyg_uint32 *)h;
166 pbase[k] = (cyg_uint32 *)j;
172 if ( (i == k) && (h > j) )
173 pbase[ i ] = (cyg_uint32 *)((h+j)/2);
175 for ( h = 0; h < NUMTESTS; h++ ) {
176 int perrors[ MEGS ] = { 0, };
177 cyg_uint32 pbadbits[ MEGS ] = { 0, };
178 for ( i = 0 ; i < INNERLOOPS; i++ ) {
179 cyg_uint32 d = 0xdeadbeef ^ ((cyg_uint32)i * 0x10001);
180 for ( k = 0; k < MEGS; k++ ) {
181 cyg_uint32 *p = pbase[k];
182 cyg_uint32 dp = d ^ (cyg_uint32)p;
184 for ( j = 0; j < WORDS; j++ )
185 p[j] = dp ^ j ^ (j << 19) ;
187 for ( k = 0; k < MEGS; k++ ) {
188 cyg_uint32 *p = pbase[k];
189 cyg_uint32 dp = d ^ (cyg_uint32)p;
191 for ( j = 0; j < WORDS; j++ )
192 if ( p[j] != (dp ^ j ^ (j << 19)) ) {
194 pbadbits[k] |= (p[j] ^ dp ^ j ^ (j << 19));
199 for ( k = 0; k < MEGS; k++ ) {
200 if ( ! pbase[k] ) continue;
201 ptotalerrors[k] += perrors[k];
203 "p %x: %d tests of %d words: %d errors, badbits %x ...totals %d tests %d errors\n",
204 pbase[k], i, j, perrors[k], pbadbits[k], totaltests, ptotalerrors[k] );
205 if ( 0 != perrors[k] )
206 CYG_TEST_FAIL( "Errors in memory test" );
211 for ( k = 0; k < MEGS; k++ ) {
212 if ( ! pbase[k] ) continue;
213 h += ptotalerrors[k] ;
216 diag_printf( "Total tests %d, total errors %d\n", j, h );
218 CYG_TEST_PASS( "Memory test all OK" );
220 CYG_TEST_EXIT("End of mem test");
227 HAL_ENABLE_INTERRUPTS();
229 #ifdef CYGPKG_HAL_ARM_EBSA285
231 i = *(cyg_uint32 *)(0x42000000 + 0x10c);
232 diag_printf( "SDRAM timing %08x\n", i );
233 for ( i = 0; i < 4; i++ ) {
234 diag_printf( "Bank %d: addrsize %08x\n", i, *(cyg_uint32 *)(0x42000000 + 0x110 + i * 4 ));
236 diag_printf( "Mem size: %08x == %d\n", hal_dram_size, hal_dram_size );