1 //==========================================================================
5 // HAL misc board support definitions
7 //==========================================================================
8 //####ECOSGPLCOPYRIGHTBEGIN####
9 // -------------------------------------------
10 // This file is part of eCos, the Embedded Configurable Operating System.
11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
12 // Copyright (C) 2002 Gary Thomas
14 // eCos is free software; you can redistribute it and/or modify it under
15 // the terms of the GNU General Public License as published by the Free
16 // Software Foundation; either version 2 or (at your option) any later version.
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20 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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24 // with eCos; if not, write to the Free Software Foundation, Inc.,
25 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
27 // As a special exception, if other files instantiate templates or use macros
28 // or inline functions from this file, or you compile this file and link it
29 // with other works to produce a work based on this file, this file does not
30 // by itself cause the resulting work to be covered by the GNU General Public
31 // License. However the source code for this file must still be made available
32 // in accordance with section (3) of the GNU General Public License.
34 // This exception does not invalidate any other reasons why a work based on
35 // this file might be covered by the GNU General Public License.
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38 // at http://sources.redhat.com/ecos/ecos-license/
39 // -------------------------------------------
40 //####ECOSGPLCOPYRIGHTEND####
41 //========================================================================*/
48 #define REG8_VAL(a) (a)
49 #define REG16_VAL(a) (a)
50 #define REG32_VAL(a) (a)
52 #define REG8_PTR(a) (a)
53 #define REG16_PTR(a) (a)
54 #define REG32_PTR(a) (a)
56 #else /* __ASSEMBLER__ */
58 extern char HAL_PLATFORM_EXTRA[];
59 #define REG8_VAL(a) ((unsigned char)(a))
60 #define REG16_VAL(a) ((unsigned short)(a))
61 #define REG32_VAL(a) ((unsigned int)(a))
63 #define REG8_PTR(a) ((volatile unsigned char *)(a))
64 #define REG16_PTR(a) ((volatile unsigned short *)(a))
65 #define REG32_PTR(a) ((volatile unsigned int *)(a))
66 #define readb(a) (*(volatile unsigned char *)(a))
67 #define readw(a) (*(volatile unsigned short *)(a))
68 #define readl(a) (*(volatile unsigned int *)(a))
69 #define writeb(v,a) (*(volatile unsigned char *)(a) = (v))
70 #define writew(v,a) (*(volatile unsigned short *)(a) = (v))
71 #define writel(v,a) (*(volatile unsigned int *)(a) = (v))
73 #endif /* __ASSEMBLER__ */
76 * Default Memory Layout Definitions
80 * Function Multiplexing Control Register (FMCR)
82 #define MX21_FMCR 0x10027814
84 * MX21 IRQ Controller Register Definitions.
86 #define MX21_AITC_BASE 0x10040000
87 #define MX21_AITC_NIMASK 0x10040004
88 #define MX21_AITC_INTTYPEH 0x10040018
89 #define MX21_AITC_INTTYPEL 0x10040014
90 #define MX21_AITC_NIPRIORITY3 0x10040030
91 #define MX21_AITC_NIPRIORITY2 0x10040034
92 #define MX21_AITC_NIPRIORITY1 0x10040038
93 #define MX21_AITC_NIPRIORITY0 0x1004003C
96 * MX21 UART Base Addresses
98 #define MX21_UART1_BASE 0x1000A000
99 #define MX21_UART2_BASE 0x1000B000
100 #define MX21_UART3_BASE 0x1000C000
101 #define MX21_UART4_BASE 0x1000D000
103 #define MX21_AIPI1_BASE 0x10000000 /* AIPI 1 */
104 #define MX21_AIPI2_BASE 0x10020000 /* AIPI 2 */
105 #define MX21_CRM_SysCtrl_BASE 0x10027800 /* system control */
106 #define CRM_SysCtrl_PCSR_Offset 0x50
108 #define MX21_MAX_BASE 0x1003F000 /* MAX */
109 #define MAX_Port0_OFFSET 0x0
110 #define MAX_Port1_OFFSET 0x100
111 #define MAX_Port2_OFFSET 0x200
112 #define MAX_Port3_OFFSET 0x300
113 #define MAX_Port4_OFFSET 0x400
114 #define MAX_Port5_OFFSET 0x500
116 #define MAX_Slave_MPR_Offset 0x0 /* Master Priority register */
117 #define MAX_Slave_AMPR_Offset 0x4 /* Alternate Master Priority register */
118 #define MAX_Slave_SGPCR_Offset 0x10 /* Slave General Purpose Control register */
119 #define MAX_Slave_ASGPCR_Offset 0x14 /* Alternate Slave General Purpose control register */
120 #define MAX_Master_MGPCR_Offset 0x800 /* Master General Purpose Control Register */
121 #define MX21_CRM_BASE 0x10027000 /* RST/CLK */
122 #define MX21_CRM_CSCR 0x00 /* clock source control reg */
123 #define MX21_CRM_MPCTL0 0x04 /* MCU & System PLL control register 0 */
124 #define MX21_CRM_MPCTL1 0x08 /* MCU & System PLL control register 1 */
125 #define MX21_CRM_SPCTL0 0x0C /* serial peripheral PLL control register 0 */
126 #define MX21_CRM_SPCTL1 0x10 /* serial peripheral PLL control register 1 */
127 #define MX21_CRM_PCDR0 0x18 /* peripheral clock divider register 0 */
128 #define MX21_CRM_PCDR1 0x1C /* peripheral clock divider register 1 */
129 #define MX21_CRM_PCCR0 0x20 /* peripheral clock control register 0 */
130 #define MX21_CRM_PCCR1 0x24 /* peripheral clock control register 1 */
131 #define MX21_CRM_CCSR 0x28 /* Clock Control Status Register */
132 #define CRM_CSCR_USBDIV (0x5<<26)
133 #define CRM_CSCR_SD_CNT (0x3<<24)
134 #define CRM_CSCR_SPLL_Restart (0x1<<22)
135 #define CRM_CSCR_MPLL_Restart (0x1<<21)
136 #define CRM_CSCR_Prescaler 0
137 #define CRM_CSCR_BCLKDIV (0x1<<10)
138 #define CRM_CSCR_IPDIV 0
139 #define CRM_CSCR_FPM_EN (0x1<<2)
140 #define CRM_CSCR_SPEN (0x1<<1)
141 #define CRM_CSCR_MPEN (0x1<<0)
143 #define CRM_MPCTL0_PD (0<<26)
144 #define CRM_MPCTL0_MFD (123<<16)
145 #define CRM_MPCTL0_MFI (7<<10)
146 #define CRM_MPCTL0_MFN 115
148 #define CRM_SPCTL0_PD (0<<26)
149 #define CRM_SPCTL0_MFD (944<<16)
150 #define CRM_SPCTL0_MFI (8<<10)
151 #define CRM_SPCTL0_MFN 551
153 #define FREQ_26MHZ 26000000
154 #define FREQ_32768HZ (32768 * 512)
155 #define FREQ_32000HZ (32000 * 512)
157 #define PLL_REF_CLK FREQ_32768HZ
158 //#define PLL_REF_CLK FREQ_26MHZ
159 //#define PLL_REF_CLK FREQ_32000HZ
162 * MX21 GPIO Register Definitions
164 #define MX21_GPIOA_BASE 0x10015000
165 #define MX21_GPIOB_BASE 0x10015100
166 #define MX21_GPIOC_BASE 0x10015200
167 #define MX21_GPIOD_BASE 0x10015300
168 #define MX21_GPIOE_BASE 0x10015400
169 #define MX21_GPIOF_BASE 0x10015500
170 #define MX21_GPIO_PMASK 0x10015600
171 #define KHwGpioDDIR 0x000 /* Data direction reg */
172 #define KHwGpioOCR1 0x004 /* Output config reg 1 */
173 #define KHwGpioOCR2 0x008 /* Output config reg 2 */
174 #define KHwGpioICONFA1 0x00C /* Input config reg A1 */
175 #define KHwGpioICONFA2 0x010 /* Input config reg A2 */
176 #define KHwGpioICONFB1 0x014 /* Input config reg B1 */
177 #define KHwGpioICONFB2 0x018 /* Input config reg B2 */
178 #define KHwGpioDR 0x01C /* Data reg */
179 #define KHwGpioGIUS 0x020 /* GPIO in use reg */
180 #define KHwGpioSSR 0x024 /* Sample startus reg */
181 #define KHwGpioICR1 0x028 /* Int config reg 1 */
182 #define KHwGpioICR2 0x02C /* Int config reg 2 */
183 #define KHwGpioIMR 0x030 /* Int mask reg */
184 #define KHwGpioISR 0x034 /* Int status reg */
185 #define KHwGpioGPR 0x038 /* Gen purpose reg */
186 #define KHwGpioSWR 0x03C /* Software reset reg */
187 #define KHwGpioPUEN 0x040 /* Pull-up enable reg */
189 #define EGpioOCR_A 0 /* External input a_IN */
190 #define EGpioOCR_B 1 /* External input b_IN */
191 #define EGpioOCR_C 2 /* External input c_IN */
192 #define EGpioOCR_DR 3 /* Data register */
193 #define EGpioICONF_In 0 /* GPIO-in */
194 #define EGpioICONF_Isr 1 /* Interrupt status register */
195 #define EGpioICONF_0 2 /* 0 */
196 #define EGpioICONF_1 3 /* 1 */
197 #define EGpioICR_PosEdge 0 /* Positive edge */
198 #define EGpioICR_NegEdge 1 /* Negative edge */
199 #define EGpioICR_PosLvl 2 /* Positive level */
200 #define EGpioICR_NegLvl 3 /* Negative level */
201 #define EGpioSWR_SWR 1 /* Software reset */
206 #define HAL_DELAY_TIMER_MX2 MX21_Timer2_BASE // use timer2 for hal_delay_us()
208 #define MX21_Timer1_BASE 0x10003000
209 #define MX21_Timer2_BASE 0x10004000
210 #define MX21_Timer3_BASE 0x10005000
211 #define KHwTimerTCL 0x00
212 #define KHwTimerTPRER 0x04
213 #define KHwTimerTCMP 0x08
214 #define KHwTimerTCR 0x0C
215 #define KHwTimerTCN 0x10
216 #define KHwTimerTSTAT 0x14
217 #define MX_STARTUP_DELAY (1000000/10) // 0.1s delay to get around the ethernet reset failure problem
219 #define MX21_PERCLK1 44333342 /* Peripheral Clock 1 */
220 #define DelayTimerPresVal 3
221 #define MX21_SI_ID_REG 0x1002780C
222 //CS_IN0 is connected to the BoardID chip on MX21 ADS board.
223 #define MX21_CS_IN0_BASE 0xCC400000
224 #define MX21_SILICONID_Rev2_x 0x001D101D
225 #define MX21_SILICONID_Rev3_0 0x101D101D
226 #define MX21_SILICONID_Rev3_1 0x201D101D
227 #define CHIP_REV_1_x 1
228 #define CHIP_REV_2_x 2
229 #define CHIP_REV_3_0 3
230 #define CHIP_REV_3_1 4
231 #define CHIP_REV_unknown 0x100
233 #define MX21_DSCR_BASE 0x10027820
245 #define WDOG_BASE_ADDR 0x10002000
247 #define ESDCTL_BASE 0xDF000000
248 #define NFC_BASE 0xDF003000
249 #define MX21_EIM_BASE 0xDF001000 /* EIM */
250 #define MX21_CS1_LOCTRL 0x0C /* CS1 lower control register */
251 #define MX21_CS1_UPCTRL 0x08 /* CS1 upper control register */
254 #define MX21_CS1_BASE 0xCC000000
257 #define CSD0_BASE_ADDR 0xC0000000
258 #define CS0_BASE_ADDR 0xC8000000
259 #define NAND_REG_BASE (NFC_BASE + 0xE00)
260 #define NFC_BUFSIZE_REG_OFF (0 + 0x00)
261 #define RAM_BUFFER_ADDRESS_REG_OFF (0 + 0x04)
262 #define NAND_FLASH_ADD_REG_OFF (0 + 0x06)
263 #define NAND_FLASH_CMD_REG_OFF (0 + 0x08)
264 #define NFC_CONFIGURATION_REG_OFF (0 + 0x0A)
265 #define ECC_STATUS_RESULT_REG_OFF (0 + 0x0C)
266 #define ECC_RSLT_MAIN_AREA_REG_OFF (0 + 0x0E)
267 #define ECC_RSLT_SPARE_AREA_REG_OFF (0 + 0x10)
268 #define NF_WR_PROT_REG_OFF (0 + 0x12)
269 #define UNLOCK_START_BLK_ADD_REG_OFF (0 + 0x14)
270 #define UNLOCK_END_BLK_ADD_REG_OFF (0 + 0x16)
271 #define NAND_FLASH_WR_PR_ST_REG_OFF (0 + 0x18)
272 #define NAND_FLASH_CONFIG1_REG_OFF (0 + 0x1A)
273 #define NAND_FLASH_CONFIG2_REG_OFF (0 + 0x1C)
274 #define RAM_BUFFER_ADDRESS_RBA_3 0x3
275 #define NFC_BUFSIZE_1KB 0x0
276 #define NFC_BUFSIZE_2KB 0x1
277 #define NFC_CONFIGURATION_UNLOCKED 0x2
278 #define ECC_STATUS_RESULT_NO_ERR 0x0
279 #define ECC_STATUS_RESULT_1BIT_ERR 0x1
280 #define ECC_STATUS_RESULT_2BIT_ERR 0x2
281 #define NF_WR_PROT_UNLOCK 0x4
282 #define NAND_FLASH_CONFIG1_FORCE_CE (1 << 7)
283 #define NAND_FLASH_CONFIG1_RST (1 << 6)
284 #define NAND_FLASH_CONFIG1_BIG (1 << 5)
285 #define NAND_FLASH_CONFIG1_INT_MSK (1 << 4)
286 #define NAND_FLASH_CONFIG1_ECC_EN (1 << 3)
287 #define NAND_FLASH_CONFIG1_SP_EN (1 << 2)
288 #define NAND_FLASH_CONFIG2_INT_DONE (1 << 15)
289 #define NAND_FLASH_CONFIG2_FDO_PAGE (0 << 3)
290 #define NAND_FLASH_CONFIG2_FDO_ID (2 << 3)
291 #define NAND_FLASH_CONFIG2_FDO_STATUS (4 << 3)
292 #define NAND_FLASH_CONFIG2_FDI_EN (1 << 2)
293 #define NAND_FLASH_CONFIG2_FADD_EN (1 << 1)
294 #define NAND_FLASH_CONFIG2_FCMD_EN (1 << 0)
295 #define FDO_PAGE_SPARE_VAL 0x8
297 #define NOR_FLASH_BOOT 0
298 #define NAND_FLASH_BOOT 0x10
299 #define SDRAM_NON_FLASH_BOOT 0x20
300 #define MMC_BOOT 0x40
301 #define MXCBOOT_FLAG_REG (MX21_AITC_BASE + 0x20)
303 #define MXCFIS_NOTHING 0x00000000
304 #define MXCFIS_NAND 0x10000000
305 #define MXCFIS_NOR 0x20000000
306 #define MXCFIS_MMC 0x40000000
307 #define MXCFIS_FLAG_REG (MX21_AITC_BASE + 0x24)
309 #define IS_BOOTING_FROM_NAND() (readl(MXCBOOT_FLAG_REG) == NAND_FLASH_BOOT)
310 #define IS_BOOTING_FROM_NOR() (readl(MXCBOOT_FLAG_REG) == NOR_FLASH_BOOT)
311 #define IS_BOOTING_FROM_SDRAM() (readl(MXCBOOT_FLAG_REG) == SDRAM_NON_FLASH_BOOT)
312 #define IS_BOOTING_FROM_MMC() (readl(MXCBOOT_FLAG_REG) == MMC_BOOT)
314 #ifndef MXCFLASH_SELECT_NAND
315 #define IS_FIS_FROM_NAND() 0
317 #define IS_FIS_FROM_NAND() (readl(MXCFIS_FLAG_REG) == MXCFIS_NAND)
320 #ifndef MXCFLASH_SELECT_NOR
321 #define IS_FIS_FROM_NOR() 0
323 #define IS_FIS_FROM_NOR() (readl(MXCFIS_FLAG_REG) == MXCFIS_NOR)
326 #ifndef MXCFLASH_SELECT_MMC
327 #define IS_FIS_FROM_MMC() 0
329 #define IS_FIS_FROM_MMC() (readl(MXCFIS_FLAG_REG) == MXCFIS_MMC)
332 #define MXC_ASSERT_NOR_BOOT() writel(MXCFIS_NOR, MXCFIS_FLAG_REG)
333 #define MXC_ASSERT_NAND_BOOT() writel(MXCFIS_NAND, MXCFIS_FLAG_REG)
334 #define MXC_ASSERT_MMC_BOOT() writel(MXCFIS_MMC, MXCFIS_FLAG_REG)
336 #define SERIAL_DOWNLOAD_MAGIC 0x000000AA
337 #define SERIAL_DOWNLOAD_MAGIC_REG MX21_AITC_NIPRIORITY3
338 #define SERIAL_DOWNLOAD_SRC_REG MX21_AITC_NIPRIORITY2
339 #define SERIAL_DOWNLOAD_TGT_REG MX21_AITC_NIPRIORITY1
340 #define SERIAL_DOWNLOAD_SZ_REG MX21_AITC_NIPRIORITY0
342 #if !defined(__ASSEMBLER__)
343 void cyg_hal_plf_serial_init(void);
344 void cyg_hal_plf_serial_stop(void);
345 void hal_delay_us(unsigned int usecs);
346 #define HAL_DELAY_US(n) hal_delay_us(n)
349 MCU_PLL = MX21_CRM_BASE + MX21_CRM_MPCTL0,
350 SER_PLL = MX21_CRM_BASE + MX21_CRM_SPCTL0,
371 typedef unsigned int nfc_setup_func_t(unsigned int, unsigned int, unsigned int, unsigned int);
373 #endif //#if !defined(__ASSEMBLER__)
375 #define HAL_MMU_OFF() \
379 "mrc p15, 0, r15, c7, c14, 3;" /*test clean and inval*/ \
382 "mcr p15,0,r0,c7,c10,4;" /*drain write buffer*/ \
383 "mcr p15,0,r0,c7,c5,0;" /* invalidate I cache */ \
384 "mrc p15,0,r0,c1,c0,0;" /* read c1 */ \
385 "bic r0,r0,#0x7;" /* disable DCache and MMU */ \
386 "bic r0,r0,#0x1000;" /* disable ICache */ \
387 "mcr p15,0,r0,c1,c0,0;" /* */ \
388 "nop;" /* flush i+d-TLBs */ \
389 "nop;" /* flush i+d-TLBs */ \
390 "nop;" /* flush i+d-TLBs */ \
393 : "r0","memory" /* clobber list */); \
396 #endif /* __HAL_SOC_H__ */