1 #ifndef CYGONCE_HAL_PLATFORM_SETUP_H
2 #define CYGONCE_HAL_PLATFORM_SETUP_H
4 /*=============================================================================
6 // hal_platform_setup.h
8 // Platform specific support for HAL (assembly code)
10 //=============================================================================
11 //####ECOSGPLCOPYRIGHTBEGIN####
12 // -------------------------------------------
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14 // Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Red Hat, Inc.
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41 // -------------------------------------------
42 //####ECOSGPLCOPYRIGHTEND####
43 //=============================================================================
44 //#####DESCRIPTIONBEGIN####
47 // Contributors: msalter
49 // Purpose: Motorola PRPMC1100 specific support routines
51 // Usage: #include <cyg/hal/hal_platform_setup.h>
52 // Only used by "vectors.S"
54 //####DESCRIPTIONEND####
56 //===========================================================================*/
58 #include <pkgconf/system.h> // System-wide configuration info
59 #include CYGBLD_HAL_VARIANT_H // Variant specific configuration
60 #include CYGBLD_HAL_PLATFORM_H // Platform specific configuration
61 #include <cyg/hal/hal_ixp425.h> // Variant specific hardware definitions
62 #include <cyg/hal/hal_mmu.h> // MMU definitions
63 #include <cyg/hal/hal_mm.h> // more MMU definitions
64 #include <cyg/hal/prpmc1100.h> // Platform specific hardware definitions
66 #if defined(CYG_HAL_STARTUP_ROM)
67 #define PLATFORM_SETUP1 _platform_setup1
68 #define PLATFORM_EXTRAS <cyg/hal/hal_platform_extras.h>
69 #define CYGHWR_HAL_ARM_HAS_MMU
71 // ------------------------------------------------------------------------
72 // Define macro used to diddle the LEDs during early initialization.
73 // Can use r0+r1. Argument in \x.
74 #define CYGHWR_LED_MACRO
77 .macro DELAY cycles, reg0
83 // ------------------------------------------------------------------------
84 // This macro represents the initial startup code for the platform
85 .macro _platform_setup1
87 #if CYGINT_HAL_ARM_BIGENDIAN
89 mrc p15, 0, r0, c1, c0, 0
91 mcr p15, 0, r0, c1, c0, 0
95 ldr r0,=(CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE|CPSR_SUPERVISOR_MODE)
98 // invalidate I & D caches & BTB
99 mcr p15, 0, r0, c7, c7, 0
102 // invalidate I & Data TLB
103 mcr p15, 0, r0, c8, c7, 0
106 // drain write and fill buffers
107 mcr p15, 0, r0, c7, c10, 4
110 // disable write buffer coalescing
111 mrc p15, 0, r0, c1, c0, 1
113 mcr p15, 0, r0, c1, c0, 1
116 // Setup chip selects
117 ldr r1, =IXP425_EXP_CFG_BASE
118 #ifdef IXP425_EXP_CS0_INIT
119 ldr r0, =IXP425_EXP_CS0_INIT
120 str r0, [r1, #IXP425_EXP_CS0]
122 #ifdef IXP425_EXP_CS1_INIT
123 ldr r0, =IXP425_EXP_CS1_INIT
124 str r0, [r1, #IXP425_EXP_CS1]
126 #ifdef IXP425_EXP_CS2_INIT
127 ldr r0, =IXP425_EXP_CS2_INIT
128 str r0, [r1, #IXP425_EXP_CS2]
130 #ifdef IXP425_EXP_CS3_INIT
131 ldr r0, =IXP425_EXP_CS3_INIT
132 str r0, [r1, #IXP425_EXP_CS3]
134 #ifdef IXP425_EXP_CS4_INIT
135 ldr r0, =IXP425_EXP_CS4_INIT
136 str r0, [r1, #IXP425_EXP_CS4]
138 #ifdef IXP425_EXP_CS5_INIT
139 ldr r0, =IXP425_EXP_CS5_INIT
140 str r0, [r1, #IXP425_EXP_CS5]
142 #ifdef IXP425_EXP_CS6_INIT
143 ldr r0, =IXP425_EXP_CS6_INIT
144 str r0, [r1, #IXP425_EXP_CS6]
146 #ifdef IXP425_EXP_CS7_INIT
147 ldr r0, =IXP425_EXP_CS7_INIT
148 str r0, [r1, #IXP425_EXP_CS7]
152 mrc p15, 0, r0, c1, c0, 0
153 orr r0, r0, #MMU_Control_I
154 mcr p15, 0, r0, c1, c0, 0
157 // Setup SDRAM controller
159 ldr r0, =IXP425_SDRAM_CFG_BASE
161 ldr r1, =IXP425_SDRAM_CONFIG_INIT
162 str r1, [r0, #IXP425_SDRAM_CONFIG]
164 // disable refresh cycles
166 str r1, [r0, #IXP425_SDRAM_REFRESH]
169 mov r1, #SDRAM_IR_NOP
170 str r1, [r0, #IXP425_SDRAM_IR]
173 // set SDRAM internal refresh val
174 ldr r1, =IXP425_SDRAM_REFRESH_CNT
175 str r1, [r0, #IXP425_SDRAM_REFRESH]
178 // send precharge-all command to close all open banks
179 mov r1, #SDRAM_IR_PRECHARGE
180 str r1, [r0, #IXP425_SDRAM_IR]
183 // provide 8 auto-refresh cycles
184 mov r1, #SDRAM_IR_AUTO_REFRESH
187 str r1, [r0, #IXP425_SDRAM_IR]
192 // set mode register in sdram
193 mov r1, #IXP425_SDRAM_SET_MODE_CMD
194 str r1, [r0, #IXP425_SDRAM_IR]
197 // start normal operation
198 mov r1, #SDRAM_IR_NORMAL
199 str r1, [r0, #IXP425_SDRAM_IR]
202 // value to load into pc to jump to real runtime address
205 // Setup EXP_CNFG0 value to switch EXP bus out of low memory
206 ldr r2, =IXP425_EXP_CFG_BASE
207 ldr r1, [r2, #IXP425_EXP_CNFG0]
208 bic r1, r1, #EXP_CNFG0_MEM_MAP
213 // Here is where we switch from boot address (0x000000000) to the
214 // actual flash runtime address. We align to cache boundary so we
215 // execute from cache during the switchover. Cachelines are 8 words.
216 str r1, [r2, #IXP425_EXP_CNFG0] // make the EXP bus switch
223 // display FFFF and loop forever.
227 // Move mmu tables into RAM so page table walks by the cpu
228 // don't interfere with FLASH programming.
230 add r2, r0, #0x4000 // End of tables
231 mov r1, #SDRAM_PHYS_BASE
232 orr r1, r1, #0x4000 // RAM tables
234 // everything can go as-is
241 mcr p15, 0, r0, c7, c10, 4 // drain the write & fill buffers
244 // Set the TTB register to DRAM mmu_table
245 ldr r0, =(SDRAM_PHYS_BASE | 0x4000) // RAM tables
246 mcr p15, 0, r0, c2, c0, 0 // load page table pointer
249 // enable permission checks in all domains
251 mcr p15, 0, r0, c3, c0, 0
255 mrc p15, 0, r0, c1, c0, 0
256 orr r0, r0, #MMU_Control_M
257 orr r0, r0, #MMU_Control_R
258 mcr p15, 0, r0, c1, c0, 0
262 mrc p15, 0, r0, c1, c0, 0
263 orr r0, r0, #MMU_Control_C
264 mcr p15, 0, r0, c1, c0, 0
267 // Enable branch target buffer
268 mrc p15, 0, r0, c1, c0, 0
269 orr r0, r0, #MMU_Control_BTB
270 mcr p15, 0, r0, c1, c0, 0
273 mcr p15, 0, r0, c7, c10, 4 // drain the write & fill buffers
276 mcr p15, 0, r0, c7, c7, 0 // flush Icache, Dcache and BTB
279 mcr p15, 0, r0, c8, c7, 0 // flush instuction and data TLBs
282 mcr p15, 0, r0, c7, c10, 4 // drain the write & fill buffers
286 ldr r1, =hal_dram_size /* [see hal_intr.h] */
290 .endm // _platform_setup1
292 #else // defined(CYG_HAL_STARTUP_ROM)
293 #define PLATFORM_SETUP1
296 #define PLATFORM_VECTORS _platform_vectors
297 .macro _platform_vectors
300 /*---------------------------------------------------------------------------*/
301 /* end of hal_platform_setup.h */
302 #endif /* CYGONCE_HAL_PLATFORM_SETUP_H */