1 #ifndef CYGONCE_KERNEL_INTR_HXX
2 #define CYGONCE_KERNEL_INTR_HXX
4 //==========================================================================
8 // Interrupt class declaration(s)
10 //==========================================================================
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43 //==========================================================================
44 //#####DESCRIPTIONBEGIN####
47 // Contributors: nickg
49 // Purpose: Define Interrupt class interfaces
50 // Description: The classes defined here provide the APIs for handling
52 // Usage: #include "intr.hxx"
55 //####DESCRIPTIONEND####
57 //==========================================================================
59 #include <cyg/kernel/ktypes.h>
61 #include <cyg/kernel/smp.hxx>
63 // -------------------------------------------------------------------------
64 // Default definitions
66 // Some HALs define the ISR table to be a different size to the number
67 // of ISR vectors. These HALs will define CYGNUM_HAL_ISR_TABLE_SIZE. All
68 // other HALs will have the table size equal to the number of vectors.
70 #ifndef CYGNUM_HAL_ISR_TABLE_SIZE
71 # define CYGNUM_HAL_ISR_TABLE_SIZE CYGNUM_HAL_ISR_COUNT
74 // -------------------------------------------------------------------------
75 // Function prototype typedefs
78 // VSR = Vector Service Routine. This is the code attached directly to an
79 // interrupt vector. It is very architecture/platform specific and usually
80 // must be written in assembler.
82 typedef void cyg_VSR();
84 // ISR = Interrupt Service Routine. This is called from the default
85 // VSR in response to an interrupt. It may access shared data but may
86 // not call kernel routines. The return value may be
87 // Cyg_Interrupt::HANDLED and/or Cyg_Interrupt::CALL_DSR.
89 typedef cyg_uint32 cyg_ISR(cyg_vector vector, CYG_ADDRWORD data);
91 // DSR = Deferred Service Routine. This is called if the ISR returns
92 // the Cyg_Interrupt::CALL_DSR bit. It is called at a "safe" point in
93 // the kernel where it may make calls on kernel routines. The count
94 // argument indicates how many times the ISR has asked for the DSR to
95 // be posted since the last time the DSR ran.
97 typedef void cyg_DSR(cyg_vector vector, cyg_ucount32 count, CYG_ADDRWORD data);
99 // -------------------------------------------------------------------------
100 // Include HAL definitions
104 #include <cyg/hal/hal_arch.h>
106 #include <cyg/hal/hal_intr.h>
108 #ifndef HAL_INTERRUPT_STACK_CALL_PENDING_DSRS
109 #define HAL_INTERRUPT_STACK_CALL_PENDING_DSRS() \
110 Cyg_Interrupt::call_pending_DSRs_inner()
113 externC void interrupt_end(
116 HAL_SavedRegisters *ctx
119 externC void cyg_interrupt_post_dsr( CYG_ADDRWORD intr_obj );
120 externC void cyg_interrupt_call_pending_DSRs( void );
122 // -------------------------------------------------------------------------
123 // Interrupt class. This both represents each interrupt and provides a static
124 // interface for controlling the interrupt hardware.
129 friend class Cyg_Scheduler;
130 friend void interrupt_end( cyg_uint32,
132 HAL_SavedRegisters *);
133 friend void cyg_interrupt_post_dsr( CYG_ADDRWORD intr_obj );
134 friend void cyg_interrupt_call_pending_DSRs( void );
136 cyg_vector vector; // Interrupt vector
138 cyg_priority priority; // Queuing priority
140 cyg_ISR *isr; // Pointer to ISR
142 cyg_DSR *dsr; // Pointer to DSR
144 CYG_ADDRWORD data; // Data pointer
148 // DSR handling interface called by the scheduler
150 // Check for pending DSRs
151 static cyg_bool DSRs_pending();
153 // Call any pending DSRs
154 static void call_pending_DSRs();
155 static void call_pending_DSRs_inner();
157 // DSR handling interface called by the scheduler and HAL
158 // interrupt arbiters.
160 void post_dsr(); // Post the DSR for this interrupt
164 // Data structures for handling DSR calls. We implement two DSR
165 // handling mechanisms, a list based one and a table based
166 // one. The list based mechanism is safe with respect to temporary
167 // overloads and will not run out of resource. However it requires
168 // extra data per interrupt object, and interrupts must be turned
169 // off briefly when delivering the DSR. The table based mechanism
170 // does not need unnecessary interrupt switching, but may be prone
171 // to overflow on overload. However, since a correctly programmed
172 // real time application should not experience such a condition,
173 // the table based mechanism is more efficient for real use. The
174 // list based mechainsm is enabled by default since it is safer to
175 // use during development.
177 #ifdef CYGIMP_KERNEL_INTERRUPTS_DSRS_TABLE
179 static Cyg_Interrupt *dsr_table[CYGNUM_KERNEL_CPU_MAX]
180 [CYGNUM_KERNEL_INTERRUPTS_DSRS_TABLE_SIZE]
181 CYGBLD_ANNOTATE_VARIABLE_INTR;
183 static cyg_ucount32 dsr_table_head[CYGNUM_KERNEL_CPU_MAX]
184 CYGBLD_ANNOTATE_VARIABLE_INTR;
186 static volatile cyg_ucount32 dsr_table_tail[CYGNUM_KERNEL_CPU_MAX]
187 CYGBLD_ANNOTATE_VARIABLE_INTR;
190 #ifdef CYGIMP_KERNEL_INTERRUPTS_DSRS_LIST
192 // Number of DSR posts made
193 volatile cyg_ucount32 dsr_count CYGBLD_ANNOTATE_VARIABLE_INTR;
196 Cyg_Interrupt* volatile next_dsr CYGBLD_ANNOTATE_VARIABLE_INTR;
198 // head of static list of pending DSRs
199 static Cyg_Interrupt* volatile dsr_list[CYGNUM_KERNEL_CPU_MAX]
200 CYGBLD_ANNOTATE_VARIABLE_INTR;
202 # ifdef CYGSEM_KERNEL_INTERRUPTS_DSRS_LIST_FIFO
203 // tail of static list of pending DSRs
204 static Cyg_Interrupt* volatile dsr_list_tail[CYGNUM_KERNEL_CPU_MAX]
205 CYGBLD_ANNOTATE_VARIABLE_INTR;
208 #endif // defined CYGIMP_KERNEL_INTERRUPTS_DSRS_LIST
210 #ifdef CYGIMP_KERNEL_INTERRUPTS_CHAIN
212 // The default mechanism for handling interrupts is to attach just
213 // one Interrupt object to each vector. In some cases, and on some
214 // hardware, this is not possible, and each vector must carry a chain
217 Cyg_Interrupt *next; // Next Interrupt in list
219 // Chaining ISR inserted in HAL vector
220 static cyg_uint32 chain_isr(cyg_vector vector, CYG_ADDRWORD data);
222 // Table of interrupt chains
223 static Cyg_Interrupt *chain_list[CYGNUM_HAL_ISR_TABLE_SIZE];
227 // Interrupt disable data. Interrupt disable can be nested. On
228 // each CPU this is controlled by disable_counter[cpu]. When the
229 // counter is first incremented from zero to one, the
230 // interrupt_disable_spinlock is claimed using spin_intsave(), the
231 // original interrupt enable state being saved in
232 // interrupt_disable_state[cpu]. When the counter is decremented
233 // back to zero the spinlock is cleared using clear_intsave().
235 // The spinlock is necessary in SMP systems since a thread
236 // accessing data shared with an ISR may be scheduled on a
237 // different CPU to the one that handles the interrupt. So, merely
238 // blocking local interrupts would be ineffective. SMP aware
239 // device drivers should either use their own spinlocks to protect
240 // data, or use the API supported by this class, via
241 // cyg_drv_isr_lock()/_unlock(). Note that it now becomes
242 // essential that ISRs do this if they are to be SMP-compatible.
244 // In a single CPU system, this mechanism reduces to just
245 // disabling/enabling interrupts.
247 // Disable level counter. This counts the number of times
248 // interrupts have been disabled.
249 static volatile cyg_int32 disable_counter[CYGNUM_KERNEL_CPU_MAX]
250 CYGBLD_ANNOTATE_VARIABLE_INTR;
252 // Interrupt disable spinlock. This is claimed by any CPU that has
253 // disabled interrupts via the Cyg_Interrupt API.
254 static Cyg_SpinLock interrupt_disable_spinlock CYGBLD_ANNOTATE_VARIABLE_INTR;
256 // Saved interrupt state. When each CPU first disables interrupts
257 // the original state of the interrupts are saved here to be
259 static CYG_INTERRUPT_STATE interrupt_disable_state[CYGNUM_KERNEL_CPU_MAX]
260 CYGBLD_ANNOTATE_VARIABLE_INTR;
265 Cyg_Interrupt // Initialize interrupt
267 cyg_vector vector, // Vector to attach to
268 cyg_priority priority, // Queue priority
269 CYG_ADDRWORD data, // Data pointer
270 cyg_ISR *isr, // Interrupt Service Routine
271 cyg_DSR *dsr // Deferred Service Routine
278 HANDLED = 1, // Interrupt was handled
279 CALL_DSR = 2 // Schedule DSR
282 // Interrupt management
284 void attach(); // Attach to vector
287 void detach(); // Detach from vector
290 // Static Interrupt management functions
292 // Get the current service routine
293 static void get_vsr(cyg_vector vector, cyg_VSR **vsr);
295 // Install a vector service routine
297 cyg_vector vector, // hardware vector to replace
298 cyg_VSR *vsr, // my new service routine
299 cyg_VSR **old = NULL // pointer to old vsr, if required
303 // Static interrupt masking functions
305 // Disable interrupts at the CPU
306 static void disable_interrupts();
308 // Re-enable CPU interrupts
309 static void enable_interrupts();
311 // Are interrupts enabled at the CPU?
312 static inline cyg_bool interrupts_enabled()
314 return (0 == disable_counter[CYG_KERNEL_CPU_THIS()]);
317 // Get the vector for the following calls
318 inline cyg_vector get_vector()
323 // Static PIC control functions
325 // Mask a specific interrupt in a PIC
326 static void mask_interrupt(cyg_vector vector);
327 // The same but not interrupt safe
328 static void mask_interrupt_intunsafe(cyg_vector vector);
331 static void unmask_interrupt(cyg_vector vector);
332 // The same but not interrupt safe
333 static void unmask_interrupt_intunsafe(cyg_vector vector);
335 // Acknowledge interrupt at PIC
336 static void acknowledge_interrupt(cyg_vector vector);
338 // Change interrupt detection at PIC
339 static void configure_interrupt(
340 cyg_vector vector, // vector to control
341 cyg_bool level, // level or edge triggered
342 cyg_bool up // hi/lo level, rising/falling edge
345 #ifdef CYGPKG_KERNEL_SMP_SUPPORT
347 // SMP support for associating an interrupt with a specific CPU.
349 static void set_cpu( cyg_vector, HAL_SMP_CPU_TYPE cpu );
350 static HAL_SMP_CPU_TYPE get_cpu( cyg_vector );
355 #ifdef CYGIMP_KERNEL_INTERRUPTS_DSRS
356 // -------------------------------------------------------------------------
357 // Check for pending DSRs
359 inline cyg_bool Cyg_Interrupt::DSRs_pending()
361 HAL_SMP_CPU_TYPE cpu = CYG_KERNEL_CPU_THIS();
362 #ifdef CYGIMP_KERNEL_INTERRUPTS_DSRS_TABLE
364 return dsr_table_head[cpu] != dsr_table_tail[cpu];
367 #ifdef CYGIMP_KERNEL_INTERRUPTS_DSRS_LIST
369 return dsr_list[cpu] != NULL;
373 #endif // CYGIMP_KERNEL_INTERRUPTS_DSRS
375 // -------------------------------------------------------------------------
376 #endif // ifndef CYGONCE_KERNEL_INTR_HXX