FDO_FLASH_STATUS = 0x0020,
};
-#define wait_for_auto_prog_done() \
- do { \
- while ((readl(NFC_IPC_REG) & NFC_IPC_AUTO_DONE) == 0) \
- {} \
- write_nfc_ip_reg((readl(NFC_IPC_REG) & ~NFC_IPC_AUTO_DONE), NFC_IPC_REG); \
- } while (0)
+#define wait_for_auto_prog_done() \
+ do { \
+ while ((nfc_reg_read(NFC_IPC_REG) & NFC_IPC_AUTO_DONE) == 0) { \
+ } \
+ write_nfc_ip_reg((nfc_reg_read(NFC_IPC_REG) & ~NFC_IPC_AUTO_DONE), NFC_IPC_REG); \
+ } while (0)
// Polls the NANDFC to wait for an operation to complete
-#define wait_op_done() \
- do { \
- while ((readl(NFC_IPC_REG) & NFC_IPC_INT) == 0) \
- {} \
- write_nfc_ip_reg(0, NFC_IPC_REG); \
- } while (0)
+#define wait_op_done() \
+ do { \
+ while ((nfc_reg_read(NFC_IPC_REG) & NFC_IPC_INT) == 0) \
+ {} \
+ write_nfc_ip_reg(0, NFC_IPC_REG); \
+ } while (0)
+
+#if 0
+#define nfc_reg_write(v, r) __nfc_reg_write(v, (void *)(r), #r, __FUNCTION__)
+static inline void __nfc_reg_write(u32 val, void *addr,
+ const char *reg, const char *fn)
+{
+ diag_printf1("%s: Writing %08x to %s[%04lx]\n", fn, val, reg,
+ (unsigned long)addr & 0x1fff);
+ writel(val, addr);
+}
+
+#define nfc_reg_read(r) __nfc_reg_read((void *)(r), #r, __FUNCTION__)
+static inline u32 __nfc_reg_read(void *addr,
+ const char *reg, const char *fn)
+{
+ u32 val;
+ val = readl(addr);
+ diag_printf1("%s: Read %08x from %s[%04lx]\n", fn, val, reg,
+ (unsigned long)addr & 0x1fff);
+ return val;
+}
+#else
+#define nfc_reg_read(r) readl(r)
+#define nfc_reg_write(v, r) writel(v, r)
+#endif
static void write_nfc_ip_reg(u32 val, u32 reg)
{
- writel(NFC_IPC_CREQ, NFC_IPC_REG);
- while((readl(NFC_IPC_REG) & NFC_IPC_CACK) == 0);
+ nfc_reg_write(NFC_IPC_CREQ, NFC_IPC_REG);
+ while((nfc_reg_read(NFC_IPC_REG) & NFC_IPC_CACK) == 0);
- writel(val, reg);
- writel((readl(NFC_IPC_REG) & ~NFC_IPC_CREQ), NFC_IPC_REG);
+ nfc_reg_write(val, reg);
+ nfc_reg_write((nfc_reg_read(NFC_IPC_REG) & ~NFC_IPC_CREQ), NFC_IPC_REG);
}
/*!
* @param ecc_en 1 - ecc enabled; 0 - ecc disabled
*/
static void NFC_DATA_OUTPUT(enum nfc_internal_buf buf_no, enum nfc_output_mode mode,
- int ecc_en)
+ int ecc_en)
{
- u32 v = readl(NFC_FLASH_CONFIG2_REG);
+ u32 v = nfc_reg_read(NFC_FLASH_CONFIG2_REG);
if ((v & NFC_FLASH_CONFIG2_ECC_EN) != 0 && ecc_en == 0) {
- write_nfc_ip_reg(v & ~NFC_FLASH_CONFIG2_ECC_EN, NFC_FLASH_CONFIG2_REG);
+ write_nfc_ip_reg(v & ~NFC_FLASH_CONFIG2_ECC_EN, NFC_FLASH_CONFIG2_REG);
}
if ((v & NFC_FLASH_CONFIG2_ECC_EN) == 0 && ecc_en != 0) {
- write_nfc_ip_reg(v | NFC_FLASH_CONFIG2_ECC_EN, NFC_FLASH_CONFIG2_REG);
+ write_nfc_ip_reg(v | NFC_FLASH_CONFIG2_ECC_EN, NFC_FLASH_CONFIG2_REG);
}
- v = readl(NAND_CONFIGURATION1_REG);
+ v = nfc_reg_read(NAND_CONFIGURATION1_REG);
if (mode == FDO_SPARE_ONLY) {
- v = (v & ~0x71) | buf_no | NAND_CONFIGURATION1_SP_EN;
+ v = (v & ~0x71) | buf_no | NAND_CONFIGURATION1_SP_EN;
} else {
- v = (v & ~0x71) | buf_no;
+ v = (v & ~0x71) | buf_no;
}
- writel(v, NAND_CONFIGURATION1_REG);
+ nfc_reg_write(v, NAND_CONFIGURATION1_REG);
- writel(mode & 0xFF, NAND_LAUNCH_REG);
+ nfc_reg_write(mode & 0xFF, NAND_LAUNCH_REG);
wait_op_done();
}
static void NFC_CMD_INPUT(u32 cmd)
{
- writel(cmd & 0xFFFF, NAND_CMD_REG);
- writel(NAND_LAUNCH_FCMD, NAND_LAUNCH_REG);
+ nfc_reg_write(cmd & 0xFFFF, NAND_CMD_REG);
+ nfc_reg_write(NAND_LAUNCH_FCMD, NAND_LAUNCH_REG);
wait_op_done();
}
{
u32 v;
- v = readl(NAND_CONFIGURATION1_REG) & (~0x7071);
+ v = nfc_reg_read(NAND_CONFIGURATION1_REG) & (~0x7071);
v |= (cs_line << 12);
- writel(v, NAND_CONFIGURATION1_REG);
+ nfc_reg_write(v, NAND_CONFIGURATION1_REG);
}
static u16 NFC_STATUS_READ(void)
int i;
#ifdef IMX51_TO_2
- return readl(NAND_STATUS_SUM_REG);
+ return nfc_reg_read(NAND_STATUS_SUM_REG);
#else
/* Cannot rely on STATUS_SUM register due to errata */
for (i = 0; i < num_of_nand_chips; i++) {
- NFC_SET_NFC_ACTIVE_CS(i);
- do {
- writel(NAND_LAUNCH_AUTO_STAT, NAND_LAUNCH_REG);
- status = (readl(NAND_CONFIGURATION1_REG) & 0x00FF0000) >> 16;
- } while ((status & 0x40) == 0); // make sure I/O 6 == 1
- /* Get Pass/Fail status */
- status = (readl(NAND_CONFIGURATION1_REG) >> 16) & 0x1;
- status_sum |= (status << i);
+ NFC_SET_NFC_ACTIVE_CS(i);
+ do {
+ nfc_reg_write(NAND_LAUNCH_AUTO_STAT, NAND_LAUNCH_REG);
+ status = (nfc_reg_read(NAND_CONFIGURATION1_REG) & 0x00FF0000) >> 16;
+ } while ((status & 0x40) == 0); // make sure I/O 6 == 1
+ /* Get Pass/Fail status */
+ status = (nfc_reg_read(NAND_CONFIGURATION1_REG) >> 16) & 0x1;
+ status_sum |= (status << i);
}
return status_sum;
#endif
int num_of_bits[] = {0, 0, 1, 0, 2, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 4};
if (ops == FLASH_Read_ID) {
- // issue addr cycle
- writel(0x0, NAND_ADD0_REG + (4 * cs_line));
- writel(NAND_LAUNCH_FADD, NAND_LAUNCH_REG);
- wait_op_done();
- return;
+ // issue addr cycle
+ nfc_reg_write(0x0, NAND_ADD0_REG + (4 * cs_line));
+ nfc_reg_write(NAND_LAUNCH_FADD, NAND_LAUNCH_REG);
+ wait_op_done();
+ return;
}
if (num_of_chips > 1) {
- page_number = (pg_no << num_of_bits[num_of_chips]) | (cs_line & (num_of_chips - 1));
+ page_number = (pg_no << num_of_bits[num_of_chips]) | (cs_line & (num_of_chips - 1));
} else {
- page_number = pg_no;
+ page_number = pg_no;
}
if (is_erase) {
- add0 = page_number;
- add8 = 0;
+ add0 = page_number;
+ add8 = 0;
} else {
- // for both read and write
- if (g_is_2k_page || g_is_4k_page) {
- // the first two addr cycles are for column addr. Page number starts
- // from the 3rd addr cycle.
- add0 = pg_off | (page_number << 16);
- add8 = page_number >> 16;
- } else {
- diag_printf("too bad, die\n");
- asm("1: b 1b");
- // For 512B page, the first addr cycle is for column addr. Page number
- // starts from the 2nd addr cycle.
- add0 = (pg_off & 0xFF) | (page_number << 8);
- add8 = page_number >> 24;
- }
+ // for both read and write
+ if (g_is_2k_page || g_is_4k_page) {
+ // the first two addr cycles are for column addr. Page number starts
+ // from the 3rd addr cycle.
+ add0 = pg_off | (page_number << 16);
+ add8 = page_number >> 16;
+ } else {
+ diag_printf("too bad, die\n");
+ asm("1: b 1b");
+ // For 512B page, the first addr cycle is for column addr. Page number
+ // starts from the 2nd addr cycle.
+ add0 = (pg_off & 0xFF) | (page_number << 8);
+ add8 = page_number >> 24;
+ }
}
- writel(add0, NAND_ADD0_REG);
- writel(add8, NAND_ADD8_REG);
+ nfc_reg_write(add0, NAND_ADD0_REG);
+ nfc_reg_write(add8, NAND_ADD8_REG);
}
/*
u32 v, res = 0;
// clear the NAND_STATUS_SUM_REG register
- writel(0, NAND_STATUS_SUM_REG);
+ nfc_reg_write(0, NAND_STATUS_SUM_REG);
// the 2nd condition is to test for unaligned page address -- ecc has to be off.
if (ecc_force == ECC_FORCE_OFF || pg_off != 0 ) {
- ecc = 0;
+ ecc = 0;
}
// Take care of config1 for RBA and SP_EN
- v = readl(NAND_CONFIGURATION1_REG) & (~0x71);
- writel(v, NAND_CONFIGURATION1_REG);
+ v = nfc_reg_read(NAND_CONFIGURATION1_REG) & (~0x71);
+ nfc_reg_write(v, NAND_CONFIGURATION1_REG);
// For ECC
- v = readl(NFC_FLASH_CONFIG2_REG) & (~NFC_FLASH_CONFIG2_ECC_EN);
+ v = nfc_reg_read(NFC_FLASH_CONFIG2_REG) & (~NFC_FLASH_CONFIG2_ECC_EN);
// setup config2 register for ECC enable or not
write_nfc_ip_reg(v | ecc, NFC_FLASH_CONFIG2_REG);
start_nfc_addr_ops(FLASH_Read_Mode1, pg_no, pg_off, 0, cs_line, num_of_chips);
if (g_is_2k_page || g_is_4k_page) {
- // combine the two commands for 2k/4k page read
- writel((FLASH_Read_Mode1_LG << 8) | FLASH_Read_Mode1, NAND_CMD_REG);
+ // combine the two commands for 2k/4k page read
+ nfc_reg_write((FLASH_Read_Mode1_LG << 8) | FLASH_Read_Mode1, NAND_CMD_REG);
} else {
- // just one command is enough for 512 page
- writel(FLASH_Read_Mode1, NAND_CMD_REG);
+ // just one command is enough for 512 page
+ nfc_reg_write(FLASH_Read_Mode1, NAND_CMD_REG);
}
// start auto-read
- writel(NAND_LAUNCH_AUTO_READ, NAND_LAUNCH_REG);
+ nfc_reg_write(NAND_LAUNCH_AUTO_READ, NAND_LAUNCH_REG);
wait_op_done();
- v = readl(NAND_STATUS_SUM_REG);
+ v = nfc_reg_read(NAND_STATUS_SUM_REG);
// test for CS0 ECC error from the STATUS_SUM register
if ((v & (0x0100 << cs_line)) != 0) {
- // clear the status
- writel((0x0100 << cs_line), NAND_STATUS_SUM_REG);
- diag_printf("ECC error from NAND_STATUS_SUM_REG(0x%x) = 0x%x\n",
- NAND_STATUS_SUM_REG, v);
- diag_printf("NAND_ECC_STATUS_RESULT_REG(0x%x) = 0x%x\n", NAND_ECC_STATUS_RESULT_REG,
- readl(NAND_ECC_STATUS_RESULT_REG));
- res = -1;
+ // clear the status
+ nfc_reg_write((0x0100 << cs_line), NAND_STATUS_SUM_REG);
+ diag_printf("ECC error from NAND_STATUS_SUM_REG(0x%x) = 0x%x\n",
+ NAND_STATUS_SUM_REG, v);
+ diag_printf("NAND_ECC_STATUS_RESULT_REG(0x%x) = 0x%x\n", NAND_ECC_STATUS_RESULT_REG,
+ nfc_reg_read(NAND_ECC_STATUS_RESULT_REG));
+ res = -1;
}
return res;
}
projects / karo-tx-redboot.git / blobdiff