sunxi: Enable non-secure access to RTC on sun6i (A31s) On the A31s the RTC is by default secured. Thus when u-boot loads the kernel in non-secure world, the RTC is unavailable. The SoC has a TrustZone Protection Controller, which can be used to enable non-secure access to the RTC. On the A31 the TZPC doesn't seem to do anything, i.e. changes to its register contents do not affect access to the RTC. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
sunxi: usb-phy: Never power off the usb ports USB devices are not really designed to get the power bounced off and on at them. Esp. USB powered harddisks do not like this. Currently we power off the USB ports both on a "usb reset" and when booting the kernel, causing the usb-power to bounce off and then back on again. This patch removes the powering off calls, fixing the undesirable power bouncing. Note this requires some special handling for the OTG port: 1) We must skip the external vbus check if we've already enabled our own vbus to avoid false positives 2) If on an usb reset we no longer detect that the id-pin is grounded, turn off vbus as that means an external vbus may be present now Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
Kill unneeded #include <linux/kconfig.h> Because the top-level Makefile forces all the source files to include include/linux/kconfig.h (see the UBOOTINCLUDE define), these includes are redundant. By the way, there are exceptions for the statement above; host programs. In fact, host tools in U-Boot depend on a particular board configuration, although I think they should not. So, some files still include <linux/config.h> to work around build errors on host tools. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Acked-by: Simon Glass <sjg@chromium.org>
sunxi: musb: Stop treating not having a vbus-det gpio as an error On some boards the otg is wired up in host-only mode in this case we have no vbus-det gpio. Stop logging an error from sunxi_usb_phy_vbus_detect() in this case, and stop treating sunxi_usb_phy_vbus_detect() returning a negative errno, as if a charger is plugged into the otg port. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Marek Vasut <marex@denx.de> Acked-by: Ian Campbell <ijc@hellion.org.uk>
sunxi: spl: Detect at runtime where SPL was read from Make possible using a single `u-boot-sunxi-with-spl.bin` binary for both NAND memory and SD card. Detection where SPL was read from is implemented in `spl_boot_device`. Signed-off-by: Daniel Kochmański <dkochmanski@turtle-solutions.eu> CC: Roy Spliet <r.spliet@ultimaker.com> Cc: Ian Campbell <ijc@hellion.org.uk> [hdegoede@redhat.com: Some small coding style fixes] Acked-by: Hans De Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
ARMv7: Factor out reusable timer_wait from sunxi/psci_sun7i.S timer_wait is moved from sunxi/psci_sun7i.S, and it can be converted completely into a reusable armv7 generic timer. LS1021A will use it as well. Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: York Sun <yorksun@freescale.com>
sunxi: rsb: Enable R_PIO clock before configuring external pins The original code was configuring the external pins after enabling the R_PIO clock, which meant the configuration never made it to the pin controller the first time in SPL. Why this was working before is uncertain. Maybe the state was left from a previous boot sequence, or RSB just happened to be the default configuration. However with some A33 chips, SPL failed to configure the PMIC. This was seen by me and Maxime on the Sinlinx SinA33 dev board. Reordering the calls fixed this. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Tested-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
sunxi: hardware-feature-specific function index defines for PORT F UART0 Commit 487b327 ("sunxi: GPIO pin mux hardware-feature-specific function index defines") renamed all GPIO index defines, but missed the PORT F UART0 setup functions. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Revert "sunxi/nand: Add support to the SPL for loading u-boot from internal NAND memory" This reverts commit f76eba38b3eda905ff3bdc18dd1240d3dcbc6e5a. This patch did not have a full and proper copyright/S-o-b chain. Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Conflicts: include/configs/sun6i.h include/configs/sun8i.h
sun6i: cpu_reset: Do not return from cpu_reset() Currently on sun6i after a "reset" the prompt returns and the user can even type stuff until the watchdog triggers and does the actual reset. This is somewhat unexpected behavior for the "reset" command, this commit adds an endless loop to wait for the watchdog to trigger so that we do not return to the prompt. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
sunxi: usb_phy: Swap check for disconnect threshold Before this commit the code for determining the disconnect threshold was checking for sun4i or sun6i assuming that those where the exception and that newer SoCs use a disconnect threshold of 2 like sun7i does. But it turns out that newer SoCs actually use a disconnect threshold of 3 and sun5i and sun7i are the exceptions, so check for those instead. Here are the settings from the various Allwinner SDK sources: sun4i-a10: USBC_Phy_Write(usbc_no, 0x2a, 3, 2); sun5i-a13: USBC_Phy_Write(usbc_no, 0x2a, 2, 2); sun6i-a31: USBC_Phy_Write(usbc_no, 0x2a, 3, 2); sun7i-a20: USBC_Phy_Write(usbc_no, 0x2a, 2, 2); sun8i-a23: USBC_Phy_Write(usbc_no, 0x2a, 3, 2); sun8i-h3: USBC_Phy_Write(usbc_no, 0x2a, 3, 2); sun9i-a80: USBC_Phy_Write(usbc_no, 0x2a, 3, 2); Note this commit makes no functional changes for sun4i - sun7i, and changes the disconnect threshold for sun8i to match what Allwinner uses. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
ARM: sunxi: Share sun6i PSCI backend with sun8i sun8i can share the PSCI backend with sun6i. Only difference is sun8i does not have CPU power clamp controls. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
ARM: sunxi: Add sun6i specific PSCI implementation This adds PSCI support for sun6i. So far it only supports the PWR_ON method. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
ARM: sunxi: Make PSCI code sun7i specific The PSCI code only works for sun7i. Rename it with _sun7i suffix, and build only if building for sun7i. This paves the way for adding PSCI support for other platforms. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
ARM: sunxi: Document registers in PSCI code The PSCI CPU_ON code accesses quite a few registers. Document their names to make it easier to cross reference. Also explain "lock cpu" and "unlock cpu" as enabling/disabling debug access. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>