mxs_gpio: correctly use the GPIO API The GPIO API expects a linear GPIO number as parameter to the gpio_*() functions. The current implementation of the mxs_gpio driver operates on iomux_cfg_t cookies instead. Therefore the 'gpio' command cannot be used with this driver. Change the driver to implement the correct API and introduce some checks to catch users that still use the old semantics. 1. assert the most sigificant bit in the iomux_cfg_t pad definitions, so that using such a cookie in place of a GPIO number will decisively generate an invalid GPIO number and flag an error at runtime. 2. introduce a compile switch CONFIG_MXS_IOMUX_COMPILE_CHECK to make the iomux_cfg_t cookie a 64 bit variable, so that passing an iomux_cfg_t value to a gpio_*() function will generate a compile time error.
fsl: common: pfuze: no use original pfuze code if DM_PMIC If enable DM PMIC and REGULATOR, we should not use original power framework. So need to comment out the pfuze code for original power framework, when CONFIG_DM_PMIC_PFUZE100 defined. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
armv7/ls1021a: allow OCRAM access permission as R/W in SPL On LS1021A Rev2.0, OCRAM's security level needs to be changed to non-secure access for SD boot. This patch will allow OCRAM access permission as R/W in SPL. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
armv7/ls1021atwr: program the regulator for deep sleep Program the external regulator to switch off voltage in deep sleep. Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com> Acked-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
imx: mx6ul_14x14_evk add basic board support 1. Add USDHC, I2C, UART, 74LV, USB, QSPI support. 2. Support SPL 3. CONFIG_MX6UL_14X14_EVK_EMMC_REWORK is introduced, this board default supports sd for usdhc2, but can do hardware rework to make usdhc2 support emmc. Boot Log: U-Boot SPL 2015.07-rc3-00124-g35d727b (Jul 20 2015 - 18:40:59) reading u-boot.img reading u-boot.img U-Boot 2015.07-rc3-00124-g35d727b (Jul 20 2015 - 18:40:59 +0800) CPU: Freescale i.MX6UL rev1.0 792 MHz (running at 396 MHz) CPU: Commercial temperature grade (0C to 95C)CPU: Thermal invalid data, fuse: 0x0 - invalid sensor device Reset cause: POR Board: MX6UL 14x14 EVK I2C: ready DRAM: 512 MiB MMC: FSL_SDHC: 0, FSL_SDHC: 1 *** Warning - bad CRC, using default environment In: serial Out: serial Err: serial Net: CPU Net Initialization Failed No ethernet found. Hit any key to stop autoboot: 0 Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
imx: mx6qpsabreauto: Add MX6QP SABREAUTO CPU3 board support 1. Add DDR script for mx6qpsabreauto board. 2. On CPU3 board, enet RGMII tx clock is from internal PLL. Set the GPR5[9] and init the enet pll output to 125Mhz. 3. On CPU3 board, SW1ABC=VDDSOC_IN, SW2=VDDARM_IN. Build target: mx6qpsabreauto_config Boot Log: U-Boot 2015.07-rc2-00071-gfd985ff (Jun 29 2015 - 22:10:55 +0800) CPU: Freescale i.MX6QP rev1.0 996 MHz (running at 792 MHz) CPU: Automotive temperature grade (-40C to 125C) at 34C Reset cause: POR Board: MX6Q-Sabreauto revA I2C: ready DRAM: 2 GiB PMIC: PFUZE100 ID=0x10 Flash: 32 MiB NAND: 0 MiB MMC: FSL_SDHC: 0 *** Warning - bad CRC, using default environment No panel detected: default to HDMI Display: HDMI (1024x768) In: serial Out: serial Err: serial Net: FEC [PRIME] Hit any key to stop autoboot: 0 Note: In this patch, we still add a new config mx6qpsabreauto_config, since SPL is not supported now, and IMX_CONFIG is needed at build time, so add this config. Future, when SPL is converted, this config can be removed. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Robin Gong <b38343@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
imx: mx6sabresd/sabreauto runtime setting fdt_file Detect the SOC and board variant at runtime and change the dtb name, but not hardcoding the fdt_file env variable. Take the following patch as a reference. Íd58699b157df75f1aa0b363ea9c21add21a0c "mx6cuboxi: Load the correct 'fdtfile' variable" Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
powerpc/T104xRDB: Remove vbank check redundant code sw variable in checkboard function is storing vbank value which can only take 3-bit value. So check of sw value for if greater than 7 is redundant. Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
powerpc/t1023rdb: eMMC boot without external SD card eMMC has no CD and WP pins, it needs to add board-specific board_mmc_getcd() and board_mmc_getwp() in SPL to support eMMC boot without external SD card inserted. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
powerpc/t1023rdb: add support for T1023RDB RevC Add support for NOR flash and GPIO/I2C switch control on RevC. - NOR support - bank0/bank4 switch - SD/eMMC switch - board version Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P5020 and P5040 Secure Boot Target is added for NAND for P5020 and P5040. The Secure boot target has already been added for P3041 by enabling CONFIG_SYS_RAMBOOT and configuring CPC as SRAM. The targets for P5020 and P5040 are added in the same manner. Signed-off-by: Saksham Jain <saksham@freescale.com> Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P3041 Secure Boot Target is added for NAND for P3041. For mpc85xx SoCs, the core begins execution from address 0xFFFFFFFC. In case of secure boot, this default address maps to Boot ROM. The Boot ROM code requires that the bootloader(U-boot) must lie in 0 to 3.5G address space i.e. 0x0 - 0xDFFFFFFF. In case of NAND Secure Boot, CONFIG_SYS_RAMBOOT is enabled and CPC is configured as SRAM. U-Boot binary will be located on SRAM configured at address 0xBFF00000. In the U-Boot code, TLB entries are created to map the virtual address 0xFFF00000 to physical address 0xBFF00000 of CPC configured as SRAM. Signed-off-by: Saksham Jain <saksham@freescale.com> Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
powerpc/t104x, t102x: Update CPC debug register value in PBI commands Update PBI command in pbi_cfg files to keep register bit to default reset value while configuring CPC as SRAM Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
powerpc/p2020rdb: fix the FDT_ERR_NOTFOUND issue Because the function ft_board_setup() delete the USB2 device node, it leads to can't find the device node and hung up. In fact only P1020RDB needs to delete the USB2 node, this patch fixes this issue. Signed-off-by: Ying Zhang <b40530@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
powerpc/T104xD4RDB: Add T104xD4RDB boards support T1040D4RDB is a Freescale reference board that hosts the T1040 SoC. T1040D4RDB is re-designed T1040RDB board with following changes : - Support of DDR4 memory - Support of 0x66 serdes protocol which can support following interfaces - 2 RGMII's on DTSEC4, DTSEC5 - 1 SGMII on DTSEC3 - Support of QE-TDM Similarily T1042D4RDB is a Freescale reference board that hosts the T1040 SoC. T1042D4RDB is re-designed T1042RDB board with following changes : - Support of DDR4 memory - Support for 0x86 serdes protocol which can support following interfaces - 2 RGMII's on DTSEC4, DTSEC5 - 3 SGMII on DTSEC1, DTSEC2 & DTSEC3 - Support of DIU Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com> Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
mx6sxsabresd: Use 'int' for return values The variable 'ret' is used to store the value returned by pfuze_mode_init(), so it should be of type 'int' instead of 'unsigned int' in order to correctly handle negative numbers. Fix the variable type. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
mx6sabresd: Use 'int' for return values The variable 'ret' is used to store the value returned by pfuze_mode_init(), so it should of type 'int' instead of 'unsigned int' in order to correctly handle negative numbers. Fix the variable type. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>