arch/arm/cpu/arm926ejs/at91/lowlevel_init.S

   1 /*
   2  * Memory Setup stuff - taken from blob memsetup.S
   3  *
   4  * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
   5  *                     Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
   6  *
   7  * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at)
   8  * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
   9  *
  10  * SPDX-License-Identifier:     GPL-2.0+
  11  */
  12
  13 #include <config.h>
  14 #include <asm/arch/hardware.h>
  15 #include <asm/arch/at91_pmc.h>
  16 #include <asm/arch/at91_wdt.h>
  17 #include <asm/arch/at91_pio.h>
  18 #include <asm/arch/at91_matrix.h>
  19 #include <asm/arch/at91sam9_sdramc.h>
  20 #include <asm/arch/at91sam9_smc.h>
  21 #include <asm/arch/at91_rstc.h>
  22 #ifdef CONFIG_ATMEL_LEGACY
  23 #include <asm/arch/at91sam9_matrix.h>
  24 #endif
  25 #ifndef CONFIG_SYS_MATRIX_EBICSA_VAL
  26 #define CONFIG_SYS_MATRIX_EBICSA_VAL CONFIG_SYS_MATRIX_EBI0CSA_VAL
  27 #endif
  28
  29 _TEXT_BASE:
  30         .word   CONFIG_SYS_TEXT_BASE
  31
  32 .globl lowlevel_init
  33 .type lowlevel_init,function
  34 lowlevel_init:
  35
  36         mov     r5, pc          /* r5 = POS1 + 4 current */
  37 POS1:
  38         ldr     r0, =POS1       /* r0 = POS1 compile */
  39         ldr     r2, _TEXT_BASE
  40         sub     r0, r0, r2      /* r0 = POS1-_TEXT_BASE (POS1 relative) */
  41         sub     r5, r5, r0      /* r0 = CONFIG_SYS_TEXT_BASE-1 */
  42         sub     r5, r5, #4      /* r1 = text base - current */
  43
  44         /* memory control configuration 1 */
  45         ldr     r0, =SMRDATA
  46         ldr     r2, =SMRDATA1
  47         ldr     r1, _TEXT_BASE
  48         sub     r0, r0, r1
  49         sub     r2, r2, r1
  50         add     r0, r0, r5
  51         add     r2, r2, r5
  52 0:
  53         /* the address */
  54         ldr     r1, [r0], #4
  55         /* the value */
  56         ldr     r3, [r0], #4
  57         str     r3, [r1]
  58         cmp     r2, r0
  59         bne     0b
  60
  61 /* ----------------------------------------------------------------------------
  62  * PMC Init Step 1.
  63  * ----------------------------------------------------------------------------
  64  * - Check if the PLL is already initialized
  65  * ----------------------------------------------------------------------------
  66  */
  67         ldr     r1, =(AT91_ASM_PMC_MCKR)
  68         ldr     r0, [r1]
  69         and     r0, r0, #3
  70         cmp     r0, #0
  71         bne     PLL_setup_end
  72
  73 /* ---------------------------------------------------------------------------
  74  * - Enable the Main Oscillator
  75  * ---------------------------------------------------------------------------
  76  */
  77         ldr     r1, =(AT91_ASM_PMC_MOR)
  78         ldr     r2, =(AT91_ASM_PMC_SR)
  79         /* Main oscillator Enable register PMC_MOR: */
  80         ldr     r0, =CONFIG_SYS_MOR_VAL
  81         str     r0, [r1]
  82
  83         /* Reading the PMC Status to detect when the Main Oscillator is enabled */
  84         mov     r4, #AT91_PMC_IXR_MOSCS
  85 MOSCS_Loop:
  86         ldr     r3, [r2]
  87         and     r3, r4, r3
  88         cmp     r3, #AT91_PMC_IXR_MOSCS
  89         bne     MOSCS_Loop
  90
  91 /* ----------------------------------------------------------------------------
  92  * PMC Init Step 2.
  93  * ----------------------------------------------------------------------------
  94  * Setup PLLA
  95  * ----------------------------------------------------------------------------
  96  */
  97         ldr     r1, =(AT91_ASM_PMC_PLLAR)
  98         ldr     r0, =CONFIG_SYS_PLLAR_VAL
  99         str     r0, [r1]
 100
 101         /* Reading the PMC Status register to detect when the PLLA is locked */
 102         mov     r4, #AT91_PMC_IXR_LOCKA
 103 MOSCS_Loop1:
 104         ldr     r3, [r2]
 105         and     r3, r4, r3
 106         cmp     r3, #AT91_PMC_IXR_LOCKA
 107         bne     MOSCS_Loop1
 108
 109 /* ----------------------------------------------------------------------------
 110  * PMC Init Step 3.
 111  * ----------------------------------------------------------------------------
 112  * - Switch on the Main Oscillator
 113  * ----------------------------------------------------------------------------
 114  */
 115         ldr     r1, =(AT91_ASM_PMC_MCKR)
 116
 117         /* -Master Clock Controller register PMC_MCKR */
 118         ldr     r0, =CONFIG_SYS_MCKR1_VAL
 119         str     r0, [r1]
 120
 121         /* Reading the PMC Status to detect when the Master clock is ready */
 122         mov     r4, #AT91_PMC_IXR_MCKRDY
 123 MCKRDY_Loop:
 124         ldr     r3, [r2]
 125         and     r3, r4, r3
 126         cmp     r3, #AT91_PMC_IXR_MCKRDY
 127         bne     MCKRDY_Loop
 128
 129         ldr     r0, =CONFIG_SYS_MCKR2_VAL
 130         str     r0, [r1]
 131
 132         /* Reading the PMC Status to detect when the Master clock is ready */
 133         mov     r4, #AT91_PMC_IXR_MCKRDY
 134 MCKRDY_Loop1:
 135         ldr     r3, [r2]
 136         and     r3, r4, r3
 137         cmp     r3, #AT91_PMC_IXR_MCKRDY
 138         bne     MCKRDY_Loop1
 139 PLL_setup_end:
 140
 141 /* ----------------------------------------------------------------------------
 142  * - memory control configuration 2
 143  * ----------------------------------------------------------------------------
 144  */
 145         ldr     r0, =(AT91_ASM_SDRAMC_TR)
 146         ldr     r1, [r0]
 147         cmp     r1, #0
 148         bne     SDRAM_setup_end
 149
 150         ldr     r0, =SMRDATA1
 151         ldr     r2, =SMRDATA2
 152         ldr     r1, _TEXT_BASE
 153         sub     r0, r0, r1
 154         sub     r2, r2, r1
 155         add     r0, r0, r5
 156         add     r2, r2, r5
 157 2:
 158         /* the address */
 159         ldr     r1, [r0], #4
 160         /* the value */
 161         ldr     r3, [r0], #4
 162         str     r3, [r1]
 163         cmp     r2, r0
 164         bne     2b
 165
 166 SDRAM_setup_end:
 167         /* everything is fine now */
 168         mov     pc, lr
 169
 170         .ltorg
 171
 172 SMRDATA:
 173         .word AT91_ASM_WDT_MR
 174         .word CONFIG_SYS_WDTC_WDMR_VAL
 175         /* configure PIOx as EBI0 D[16-31] */
 176 #if defined(CONFIG_AT91SAM9263)
 177         .word AT91_ASM_PIOD_PDR
 178         .word CONFIG_SYS_PIOD_PDR_VAL1
 179         .word AT91_ASM_PIOD_PUDR
 180         .word CONFIG_SYS_PIOD_PPUDR_VAL
 181         .word AT91_ASM_PIOD_ASR
 182         .word CONFIG_SYS_PIOD_PPUDR_VAL
 183 #elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) \
 184         || defined(CONFIG_AT91SAM9G20)
 185         .word AT91_ASM_PIOC_PDR
 186         .word CONFIG_SYS_PIOC_PDR_VAL1
 187         .word AT91_ASM_PIOC_PUDR
 188         .word CONFIG_SYS_PIOC_PPUDR_VAL
 189 #endif
 190         .word AT91_ASM_MATRIX_CSA0
 191         .word CONFIG_SYS_MATRIX_EBICSA_VAL
 192
 193         /* flash */
 194         .word AT91_ASM_SMC_MODE0
 195         .word CONFIG_SYS_SMC0_MODE0_VAL
 196
 197         .word AT91_ASM_SMC_CYCLE0
 198         .word CONFIG_SYS_SMC0_CYCLE0_VAL
 199
 200         .word AT91_ASM_SMC_PULSE0
 201         .word CONFIG_SYS_SMC0_PULSE0_VAL
 202
 203         .word AT91_ASM_SMC_SETUP0
 204         .word CONFIG_SYS_SMC0_SETUP0_VAL
 205
 206 SMRDATA1:
 207         .word AT91_ASM_SDRAMC_MR
 208         .word CONFIG_SYS_SDRC_MR_VAL1
 209         .word AT91_ASM_SDRAMC_TR
 210         .word CONFIG_SYS_SDRC_TR_VAL1
 211         .word AT91_ASM_SDRAMC_CR
 212         .word CONFIG_SYS_SDRC_CR_VAL
 213         .word AT91_ASM_SDRAMC_MDR
 214         .word CONFIG_SYS_SDRC_MDR_VAL
 215         .word AT91_ASM_SDRAMC_MR
 216         .word CONFIG_SYS_SDRC_MR_VAL2
 217         .word CONFIG_SYS_SDRAM_BASE
 218         .word CONFIG_SYS_SDRAM_VAL1
 219         .word AT91_ASM_SDRAMC_MR
 220         .word CONFIG_SYS_SDRC_MR_VAL3
 221         .word CONFIG_SYS_SDRAM_BASE
 222         .word CONFIG_SYS_SDRAM_VAL2
 223         .word CONFIG_SYS_SDRAM_BASE
 224         .word CONFIG_SYS_SDRAM_VAL3
 225         .word CONFIG_SYS_SDRAM_BASE
 226         .word CONFIG_SYS_SDRAM_VAL4
 227         .word CONFIG_SYS_SDRAM_BASE
 228         .word CONFIG_SYS_SDRAM_VAL5
 229         .word CONFIG_SYS_SDRAM_BASE
 230         .word CONFIG_SYS_SDRAM_VAL6
 231         .word CONFIG_SYS_SDRAM_BASE
 232         .word CONFIG_SYS_SDRAM_VAL7
 233         .word CONFIG_SYS_SDRAM_BASE
 234         .word CONFIG_SYS_SDRAM_VAL8
 235         .word CONFIG_SYS_SDRAM_BASE
 236         .word CONFIG_SYS_SDRAM_VAL9
 237         .word AT91_ASM_SDRAMC_MR
 238         .word CONFIG_SYS_SDRC_MR_VAL4
 239         .word CONFIG_SYS_SDRAM_BASE
 240         .word CONFIG_SYS_SDRAM_VAL10
 241         .word AT91_ASM_SDRAMC_MR
 242         .word CONFIG_SYS_SDRC_MR_VAL5
 243         .word CONFIG_SYS_SDRAM_BASE
 244         .word CONFIG_SYS_SDRAM_VAL11
 245         .word AT91_ASM_SDRAMC_TR
 246         .word CONFIG_SYS_SDRC_TR_VAL2
 247         .word CONFIG_SYS_SDRAM_BASE
 248         .word CONFIG_SYS_SDRAM_VAL12
 249         /* User reset enable*/
 250         .word AT91_ASM_RSTC_MR
 251         .word CONFIG_SYS_RSTC_RMR_VAL
 252 #ifdef CONFIG_SYS_MATRIX_MCFG_REMAP
 253         /* MATRIX_MCFG - REMAP all masters */
 254         .word AT91_ASM_MATRIX_MCFG
 255         .word 0x1FF
 256 #endif
 257 SMRDATA2:
 258         .word 0