arch/arm/cpu/arm926ejs/davinci/dm365_lowlevel.c

   1 /*
   2  * SoC-specific lowlevel code for tms320dm365 and similar chips
   3  * Actually used for booting from NAND with nand_spl.
   4  *
   5  * Copyright (C) 2011
   6  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10 #include <common.h>
  11 #include <nand.h>
  12 #include <ns16550.h>
  13 #include <post.h>
  14 #include <asm/arch/dm365_lowlevel.h>
  15 #include <asm/arch/hardware.h>
  16
  17 void dm365_waitloop(unsigned long loopcnt)
  18 {
  19         unsigned long   i;
  20
  21         for (i = 0; i < loopcnt; i++)
  22                 asm("   NOP");
  23 }
  24
  25 int dm365_pll1_init(unsigned long pllmult, unsigned long prediv)
  26 {
  27         unsigned int clksrc = 0x0;
  28
  29         /* Power up the PLL */
  30         clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLPWRDN);
  31
  32         clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_RES_9);
  33         setbits_le32(&dv_pll0_regs->pllctl,
  34                 clksrc << PLLCTL_CLOCK_MODE_SHIFT);
  35
  36         /*
  37          * Set PLLENSRC '0', PLL Enable(PLLEN) selection is controlled
  38          * through MMR
  39          */
  40         clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLENSRC);
  41
  42         /* Set PLLEN=0 => PLL BYPASS MODE */
  43         clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLEN);
  44
  45         dm365_waitloop(150);
  46
  47          /* PLLRST=1(reset assert) */
  48         setbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLRST);
  49
  50         dm365_waitloop(300);
  51
  52         /*Bring PLL out of Reset*/
  53         clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLRST);
  54
  55         /* Program the Multiper and Pre-Divider for PLL1 */
  56         writel(pllmult, &dv_pll0_regs->pllm);
  57         writel(prediv, &dv_pll0_regs->prediv);
  58
  59         /* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 1 */
  60         writel(PLLSECCTL_STOPMODE | PLLSECCTL_TENABLEDIV | PLLSECCTL_TENABLE |
  61                 PLLSECCTL_TINITZ, &dv_pll0_regs->secctl);
  62         /* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 0 */
  63         writel(PLLSECCTL_STOPMODE | PLLSECCTL_TENABLEDIV | PLLSECCTL_TENABLE,
  64                 &dv_pll0_regs->secctl);
  65         /* Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 0 */
  66         writel(PLLSECCTL_STOPMODE, &dv_pll0_regs->secctl);
  67         /* Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 1 */
  68         writel(PLLSECCTL_STOPMODE | PLLSECCTL_TINITZ, &dv_pll0_regs->secctl);
  69
  70         /* Program the PostDiv for PLL1 */
  71         writel(PLL_POSTDEN, &dv_pll0_regs->postdiv);
  72
  73         /* Post divider setting for PLL1 */
  74         writel(CONFIG_SYS_DM36x_PLL1_PLLDIV1, &dv_pll0_regs->plldiv1);
  75         writel(CONFIG_SYS_DM36x_PLL1_PLLDIV2, &dv_pll0_regs->plldiv2);
  76         writel(CONFIG_SYS_DM36x_PLL1_PLLDIV3, &dv_pll0_regs->plldiv3);
  77         writel(CONFIG_SYS_DM36x_PLL1_PLLDIV4, &dv_pll0_regs->plldiv4);
  78         writel(CONFIG_SYS_DM36x_PLL1_PLLDIV5, &dv_pll0_regs->plldiv5);
  79         writel(CONFIG_SYS_DM36x_PLL1_PLLDIV6, &dv_pll0_regs->plldiv6);
  80         writel(CONFIG_SYS_DM36x_PLL1_PLLDIV7, &dv_pll0_regs->plldiv7);
  81         writel(CONFIG_SYS_DM36x_PLL1_PLLDIV8, &dv_pll0_regs->plldiv8);
  82         writel(CONFIG_SYS_DM36x_PLL1_PLLDIV9, &dv_pll0_regs->plldiv9);
  83
  84         dm365_waitloop(300);
  85
  86         /* Set the GOSET bit */
  87         writel(PLLCMD_GOSET, &dv_pll0_regs->pllcmd); /* Go */
  88
  89         dm365_waitloop(300);
  90
  91         /* Wait for PLL to LOCK */
  92         while (!((readl(&dv_sys_module_regs->pll0_config) & PLL0_LOCK)
  93                 == PLL0_LOCK))
  94                 ;
  95
  96         /* Enable the PLL Bit of PLLCTL*/
  97         setbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLEN);
  98
  99         return 0;
 100 }
 101
 102 int dm365_pll2_init(unsigned long pllm, unsigned long prediv)
 103 {
 104         unsigned int clksrc = 0x0;
 105
 106         /* Power up the PLL*/
 107         clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLPWRDN);
 108
 109         /*
 110          * Select the Clock Mode as Onchip Oscilator or External Clock on
 111          * MXI pin
 112          * VDB has input on MXI pin
 113          */
 114         clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_RES_9);
 115         setbits_le32(&dv_pll1_regs->pllctl,
 116                 clksrc << PLLCTL_CLOCK_MODE_SHIFT);
 117
 118         /*
 119          * Set PLLENSRC '0', PLL Enable(PLLEN) selection is controlled
 120          * through MMR
 121          */
 122         clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLENSRC);
 123
 124         /* Set PLLEN=0 => PLL BYPASS MODE */
 125         clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLEN);
 126
 127         dm365_waitloop(50);
 128
 129          /* PLLRST=1(reset assert) */
 130         setbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLRST);
 131
 132         dm365_waitloop(300);
 133
 134         /* Bring PLL out of Reset */
 135         clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLRST);
 136
 137         /* Program the Multiper and Pre-Divider for PLL2 */
 138         writel(pllm, &dv_pll1_regs->pllm);
 139         writel(prediv, &dv_pll1_regs->prediv);
 140
 141         writel(PLL_POSTDEN, &dv_pll1_regs->postdiv);
 142
 143         /* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 1 */
 144         writel(PLLSECCTL_STOPMODE | PLLSECCTL_TENABLEDIV | PLLSECCTL_TENABLE |
 145                 PLLSECCTL_TINITZ, &dv_pll1_regs->secctl);
 146         /* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 0 */
 147         writel(PLLSECCTL_STOPMODE | PLLSECCTL_TENABLEDIV | PLLSECCTL_TENABLE,
 148                 &dv_pll1_regs->secctl);
 149         /* Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 0 */
 150         writel(PLLSECCTL_STOPMODE, &dv_pll1_regs->secctl);
 151         /* Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 1 */
 152         writel(PLLSECCTL_STOPMODE | PLLSECCTL_TINITZ, &dv_pll1_regs->secctl);
 153
 154         /* Post divider setting for PLL2 */
 155         writel(CONFIG_SYS_DM36x_PLL2_PLLDIV1, &dv_pll1_regs->plldiv1);
 156         writel(CONFIG_SYS_DM36x_PLL2_PLLDIV2, &dv_pll1_regs->plldiv2);
 157         writel(CONFIG_SYS_DM36x_PLL2_PLLDIV3, &dv_pll1_regs->plldiv3);
 158         writel(CONFIG_SYS_DM36x_PLL2_PLLDIV4, &dv_pll1_regs->plldiv4);
 159         writel(CONFIG_SYS_DM36x_PLL2_PLLDIV5, &dv_pll1_regs->plldiv5);
 160
 161         /* GoCmd for PostDivider to take effect */
 162         writel(PLLCMD_GOSET, &dv_pll1_regs->pllcmd);
 163
 164         dm365_waitloop(150);
 165
 166         /* Wait for PLL to LOCK */
 167         while (!((readl(&dv_sys_module_regs->pll1_config) & PLL1_LOCK)
 168                 == PLL1_LOCK))
 169                 ;
 170
 171         dm365_waitloop(4100);
 172
 173         /* Enable the PLL2 */
 174         setbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLEN);
 175
 176         /* do this after PLL's have been set up */
 177         writel(CONFIG_SYS_DM36x_PERI_CLK_CTRL,
 178                 &dv_sys_module_regs->peri_clkctl);
 179
 180         return 0;
 181 }
 182
 183 int dm365_ddr_setup(void)
 184 {
 185         lpsc_on(DAVINCI_LPSC_DDR_EMIF);
 186         clrbits_le32(&dv_sys_module_regs->vtpiocr,
 187                 VPTIO_IOPWRDN | VPTIO_CLRZ | VPTIO_LOCK | VPTIO_PWRDN);
 188
 189         /* Set bit CLRZ (bit 13) */
 190         setbits_le32(&dv_sys_module_regs->vtpiocr, VPTIO_CLRZ);
 191
 192         /* Check VTP READY Status */
 193         while (!(readl(&dv_sys_module_regs->vtpiocr) & VPTIO_RDY))
 194                 ;
 195
 196         /* Set bit VTP_IOPWRDWN bit 14 for DDR input buffers) */
 197         setbits_le32(&dv_sys_module_regs->vtpiocr, VPTIO_IOPWRDN);
 198
 199         /* Set bit LOCK(bit7) */
 200         setbits_le32(&dv_sys_module_regs->vtpiocr, VPTIO_LOCK);
 201
 202         /*
 203          * Powerdown VTP as it is locked (bit 6)
 204          * Set bit VTP_IOPWRDWN bit 14 for DDR input buffers)
 205          */
 206         setbits_le32(&dv_sys_module_regs->vtpiocr,
 207                 VPTIO_IOPWRDN | VPTIO_PWRDN);
 208
 209         /* Wait for calibration to complete */
 210         dm365_waitloop(150);
 211
 212         /* Set the DDR2 to synreset, then enable it again */
 213         lpsc_syncreset(DAVINCI_LPSC_DDR_EMIF);
 214         lpsc_on(DAVINCI_LPSC_DDR_EMIF);
 215
 216         writel(CONFIG_SYS_DM36x_DDR2_DDRPHYCR, &dv_ddr2_regs_ctrl->ddrphycr);
 217
 218         /* Program SDRAM Bank Config Register */
 219         writel((CONFIG_SYS_DM36x_DDR2_SDBCR | DV_DDR_BOOTUNLOCK),
 220                 &dv_ddr2_regs_ctrl->sdbcr);
 221         writel((CONFIG_SYS_DM36x_DDR2_SDBCR | DV_DDR_TIMUNLOCK),
 222                 &dv_ddr2_regs_ctrl->sdbcr);
 223
 224         /* Program SDRAM Timing Control Register1 */
 225         writel(CONFIG_SYS_DM36x_DDR2_SDTIMR, &dv_ddr2_regs_ctrl->sdtimr);
 226         /* Program SDRAM Timing Control Register2 */
 227         writel(CONFIG_SYS_DM36x_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2);
 228
 229         writel(CONFIG_SYS_DM36x_DDR2_PBBPR, &dv_ddr2_regs_ctrl->pbbpr);
 230
 231         writel(CONFIG_SYS_DM36x_DDR2_SDBCR, &dv_ddr2_regs_ctrl->sdbcr);
 232
 233         /* Program SDRAM Refresh Control Register */
 234         writel(CONFIG_SYS_DM36x_DDR2_SDRCR, &dv_ddr2_regs_ctrl->sdrcr);
 235
 236         lpsc_syncreset(DAVINCI_LPSC_DDR_EMIF);
 237         lpsc_on(DAVINCI_LPSC_DDR_EMIF);
 238
 239         return 0;
 240 }
 241
 242 static void dm365_vpss_sync_reset(void)
 243 {
 244         unsigned int PdNum = 0;
 245
 246         /* VPSS_CLKMD 1:1 */
 247         setbits_le32(&dv_sys_module_regs->vpss_clkctl,
 248                 VPSS_CLK_CTL_VPSS_CLKMD);
 249
 250         /* LPSC SyncReset DDR Clock Enable */
 251         writel(((readl(&dv_psc_regs->mdctl[DAVINCI_LPSC_VPSSMASTER]) &
 252                 ~PSC_MD_STATE_MSK) | PSC_SYNCRESET),
 253                 &dv_psc_regs->mdctl[DAVINCI_LPSC_VPSSMASTER]);
 254
 255         writel((1 << PdNum), &dv_psc_regs->ptcmd);
 256
 257         while (!(((readl(&dv_psc_regs->ptstat) >> PdNum) & PSC_GOSTAT) == 0))
 258                 ;
 259         while (!((readl(&dv_psc_regs->mdstat[DAVINCI_LPSC_VPSSMASTER]) &
 260                 PSC_MD_STATE_MSK) == PSC_SYNCRESET))
 261                 ;
 262 }
 263
 264 static void dm365_por_reset(void)
 265 {
 266         struct davinci_timer *wdog =
 267                 (struct davinci_timer *)DAVINCI_WDOG_BASE;
 268
 269         if (readl(&dv_pll0_regs->rstype) &
 270                 (PLL_RSTYPE_POR | PLL_RSTYPE_XWRST)) {
 271                 dm365_vpss_sync_reset();
 272
 273                 writel(DV_TMPBUF_VAL, TMPBUF);
 274                 setbits_le32(TMPSTATUS, FLAG_PORRST);
 275                 writel(DV_WDT_ENABLE_SYS_RESET, &wdog->na1);
 276                 writel(DV_WDT_TRIGGER_SYS_RESET, &wdog->na2);
 277
 278                 while (1);
 279         }
 280 }
 281
 282 static void dm365_wdt_reset(void)
 283 {
 284         struct davinci_timer *wdog =
 285                 (struct davinci_timer *)DAVINCI_WDOG_BASE;
 286
 287         if (readl(TMPBUF) != DV_TMPBUF_VAL) {
 288                 writel(DV_TMPBUF_VAL, TMPBUF);
 289                 setbits_le32(TMPSTATUS, FLAG_PORRST);
 290                 setbits_le32(TMPSTATUS, FLAG_FLGOFF);
 291
 292                 dm365_waitloop(100);
 293
 294                 dm365_vpss_sync_reset();
 295
 296                 writel(DV_WDT_ENABLE_SYS_RESET, &wdog->na1);
 297                 writel(DV_WDT_TRIGGER_SYS_RESET, &wdog->na2);
 298
 299                 while (1);
 300         }
 301 }
 302
 303 static void dm365_wdt_flag_on(void)
 304 {
 305         /* VPSS_CLKMD 1:2 */
 306         clrbits_le32(&dv_sys_module_regs->vpss_clkctl,
 307                 VPSS_CLK_CTL_VPSS_CLKMD);
 308         writel(0, TMPBUF);
 309         setbits_le32(TMPSTATUS, FLAG_FLGON);
 310 }
 311
 312 void dm365_psc_init(void)
 313 {
 314         unsigned char i = 0;
 315         unsigned char lpsc_start;
 316         unsigned char lpsc_end, lpscgroup, lpscmin, lpscmax;
 317         unsigned int  PdNum = 0;
 318
 319         lpscmin = 0;
 320         lpscmax = 2;
 321
 322         for (lpscgroup = lpscmin; lpscgroup <= lpscmax; lpscgroup++) {
 323                 if (lpscgroup == 0) {
 324                         /* Enabling LPSC 3 to 28 SCR first */
 325                         lpsc_start = DAVINCI_LPSC_VPSSMSTR;
 326                         lpsc_end   = DAVINCI_LPSC_TIMER1;
 327                 } else if (lpscgroup == 1) { /* Skip locked LPSCs [29-37] */
 328                         lpsc_start = DAVINCI_LPSC_CFG5;
 329                         lpsc_end   = DAVINCI_LPSC_VPSSMASTER;
 330                 } else {
 331                         lpsc_start = DAVINCI_LPSC_MJCP;
 332                         lpsc_end   = DAVINCI_LPSC_HDVICP;
 333                 }
 334
 335                 /* NEXT=0x3, Enable LPSC's */
 336                 for (i = lpsc_start; i <= lpsc_end; i++)
 337                         setbits_le32(&dv_psc_regs->mdctl[i], PSC_ENABLE);
 338
 339                 /*
 340                  * Program goctl to start transition sequence for LPSCs
 341                  * CSL_PSC_0_REGS->PTCMD = (1<<PdNum); Kick off Power
 342                  * Domain 0 Modules
 343                  */
 344                 writel((1 << PdNum), &dv_psc_regs->ptcmd);
 345
 346                 /*
 347                  * Wait for GOSTAT = NO TRANSITION from PSC for Powerdomain 0
 348                  */
 349                 while (!(((readl(&dv_psc_regs->ptstat) >> PdNum) & PSC_GOSTAT)
 350                         == 0))
 351                         ;
 352
 353                 /* Wait for MODSTAT = ENABLE from LPSC's */
 354                 for (i = lpsc_start; i <= lpsc_end; i++)
 355                         while (!((readl(&dv_psc_regs->mdstat[i]) &
 356                                 PSC_MD_STATE_MSK) == PSC_ENABLE))
 357                                 ;
 358         }
 359 }
 360
 361 static void dm365_emif_init(void)
 362 {
 363         writel(CONFIG_SYS_DM36x_AWCCR, &davinci_emif_regs->awccr);
 364         writel(CONFIG_SYS_DM36x_AB1CR, &davinci_emif_regs->ab1cr);
 365
 366         setbits_le32(&davinci_emif_regs->nandfcr, DAVINCI_NANDFCR_CS2NAND);
 367
 368         writel(CONFIG_SYS_DM36x_AB2CR, &davinci_emif_regs->ab2cr);
 369
 370         return;
 371 }
 372
 373 void dm365_pinmux_ctl(unsigned long offset, unsigned long mask,
 374         unsigned long value)
 375 {
 376         clrbits_le32(&dv_sys_module_regs->pinmux[offset], mask);
 377         setbits_le32(&dv_sys_module_regs->pinmux[offset], (mask & value));
 378 }
 379
 380 __attribute__((weak))
 381 void board_gpio_init(void)
 382 {
 383         return;
 384 }
 385
 386 #if defined(CONFIG_POST)
 387 int post_log(char *format, ...)
 388 {
 389         return 0;
 390 }
 391 #endif
 392
 393 void dm36x_lowlevel_init(ulong bootflag)
 394 {
 395         struct davinci_uart_ctrl_regs *davinci_uart_ctrl_regs =
 396                 (struct davinci_uart_ctrl_regs *)(CONFIG_SYS_NS16550_COM1 +
 397                 DAVINCI_UART_CTRL_BASE);
 398
 399         /* Mask all interrupts */
 400         writel(DV_AINTC_INTCTL_IDMODE, &dv_aintc_regs->intctl);
 401         writel(0x0, &dv_aintc_regs->eabase);
 402         writel(0x0, &dv_aintc_regs->eint0);
 403         writel(0x0, &dv_aintc_regs->eint1);
 404
 405         /* Clear all interrupts */
 406         writel(0xffffffff, &dv_aintc_regs->fiq0);
 407         writel(0xffffffff, &dv_aintc_regs->fiq1);
 408         writel(0xffffffff, &dv_aintc_regs->irq0);
 409         writel(0xffffffff, &dv_aintc_regs->irq1);
 410
 411         dm365_por_reset();
 412         dm365_wdt_reset();
 413
 414         /* System PSC setup - enable all */
 415         dm365_psc_init();
 416
 417         /* Setup Pinmux */
 418         dm365_pinmux_ctl(0, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX0);
 419         dm365_pinmux_ctl(1, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX1);
 420         dm365_pinmux_ctl(2, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX2);
 421         dm365_pinmux_ctl(3, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX3);
 422         dm365_pinmux_ctl(4, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX4);
 423
 424         /* PLL setup */
 425         dm365_pll1_init(CONFIG_SYS_DM36x_PLL1_PLLM,
 426                 CONFIG_SYS_DM36x_PLL1_PREDIV);
 427         dm365_pll2_init(CONFIG_SYS_DM36x_PLL2_PLLM,
 428                 CONFIG_SYS_DM36x_PLL2_PREDIV);
 429
 430         /* GPIO setup */
 431         board_gpio_init();
 432
 433         NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM1),
 434                         CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
 435
 436         /*
 437          * Fix Power and Emulation Management Register
 438          * see sprufh2.pdf page 38 Table 22
 439          */
 440         writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
 441                 DAVINCI_UART_PWREMU_MGMT_UTRST),
 442                &davinci_uart_ctrl_regs->pwremu_mgmt);
 443
 444         puts("ddr init\n");
 445         dm365_ddr_setup();
 446
 447         puts("emif init\n");
 448         dm365_emif_init();
 449
 450         dm365_wdt_flag_on();
 451
 452 #if defined(CONFIG_POST)
 453         /*
 454          * Do memory tests, calls arch_memory_failure_handle()
 455          * if error detected.
 456          */
 457         memory_post_test(0);
 458 #endif
 459 }