2 * Freescale i.MX28 Boot PMIC init
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 * on behalf of DENX Software Engineering GmbH
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #include <asm/arch/imx-regs.h>
33 #ifdef CONFIG_SYS_SPL_VDDD_VAL
34 #define VDDD_VAL CONFIG_SYS_SPL_VDDD_VAL
38 #ifdef CONFIG_SYS_SPL_VDDIO_VAL
39 #define VDDIO_VAL CONFIG_SYS_SPL_VDDIO_VAL
41 #define VDDIO_VAL 3300
43 #ifdef CONFIG_SYS_SPL_VDDA_VAL
44 #define VDDA_VAL CONFIG_SYS_SPL_VDDA_VAL
48 #ifdef CONFIG_SYS_SPL_VDDMEM_VAL
49 #define VDDMEM_VAL CONFIG_SYS_SPL_VDDMEM_VAL
51 #define VDDMEM_VAL 1500
54 #ifdef CONFIG_SYS_SPL_VDDD_BO_VAL
55 #define VDDD_BO_VAL CONFIG_SYS_SPL_VDDD_BO_VAL
57 #define VDDD_BO_VAL 150
59 #ifdef CONFIG_SYS_SPL_VDDIO_BO_VAL
60 #define VDDIO_BO_VAL CONFIG_SYS_SPL_VDDIO_BO_VAL
62 #define VDDIO_BO_VAL 150
64 #ifdef CONFIG_SYS_SPL_VDDA_BO_VAL
65 #define VDDA_BO_VAL CONFIG_SYS_SPL_VDDA_BO_VAL
67 #define VDDA_BO_VAL 175
69 #ifdef CONFIG_SYS_SPL_VDDMEM_BO_VAL
70 #define VDDMEM_BO_VAL CONFIG_SYS_SPL_VDDMEM_BO_VAL
72 #define VDDMEM_BO_VAL 25
75 #ifdef CONFIG_SYS_SPL_BATT_BO_LEVEL
76 #if CONFIG_SYS_SPL_BATT_BO_LEVEL < 2400 || CONFIG_SYS_SPL_BATT_BO_LEVEL > 3640
77 #error CONFIG_SYS_SPL_BATT_BO_LEVEL out of range
79 #define BATT_BO_VAL (((CONFIG_SYS_SPL_BATT_BO_LEVEL) - 2400) / 40)
81 /* Brownout default at 3V */
82 #define BATT_BO_VAL ((3000 - 2400) / 40)
85 #ifdef CONFIG_SYS_SPL_FIXED_BATT_SUPPLY
86 static const int fixed_batt_supply = 1;
88 static const int fixed_batt_supply;
91 static struct mxs_power_regs *power_regs = (void *)MXS_POWER_BASE;
93 static void mxs_power_clock2xtal(void)
95 struct mxs_clkctrl_regs *clkctrl_regs =
96 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
98 /* Set XTAL as CPU reference clock */
99 writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
100 &clkctrl_regs->hw_clkctrl_clkseq_set);
103 static void mxs_power_clock2pll(void)
105 struct mxs_clkctrl_regs *clkctrl_regs =
106 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
108 setbits_le32(&clkctrl_regs->hw_clkctrl_pll0ctrl0,
109 CLKCTRL_PLL0CTRL0_POWER);
111 setbits_le32(&clkctrl_regs->hw_clkctrl_clkseq,
112 CLKCTRL_CLKSEQ_BYPASS_CPU);
115 static void mxs_power_clear_auto_restart(void)
117 struct mxs_rtc_regs *rtc_regs =
118 (struct mxs_rtc_regs *)MXS_RTC_BASE;
120 writel(RTC_CTRL_SFTRST, &rtc_regs->hw_rtc_ctrl_clr);
121 while (readl(&rtc_regs->hw_rtc_ctrl) & RTC_CTRL_SFTRST)
124 writel(RTC_CTRL_CLKGATE, &rtc_regs->hw_rtc_ctrl_clr);
125 while (readl(&rtc_regs->hw_rtc_ctrl) & RTC_CTRL_CLKGATE)
129 * Due to the hardware design bug of mx28 EVK-A
130 * we need to set the AUTO_RESTART bit.
132 if (readl(&rtc_regs->hw_rtc_persistent0) & RTC_PERSISTENT0_AUTO_RESTART)
135 while (readl(&rtc_regs->hw_rtc_stat) & RTC_STAT_NEW_REGS_MASK)
138 setbits_le32(&rtc_regs->hw_rtc_persistent0,
139 RTC_PERSISTENT0_AUTO_RESTART);
140 while (readl(&rtc_regs->hw_rtc_stat) & RTC_STAT_NEW_REGS_MASK)
143 writel(RTC_CTRL_FORCE_UPDATE, &rtc_regs->hw_rtc_ctrl_set);
144 while (readl(&rtc_regs->hw_rtc_stat) & RTC_STAT_STALE_REGS_MASK)
148 static void mxs_power_set_linreg(void)
150 /* Set linear regulator 25mV below switching converter */
151 clrsetbits_le32(&power_regs->hw_power_vdddctrl,
152 POWER_VDDDCTRL_LINREG_OFFSET_MASK,
153 POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW);
155 clrsetbits_le32(&power_regs->hw_power_vddactrl,
156 POWER_VDDACTRL_LINREG_OFFSET_MASK,
157 POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW);
159 clrsetbits_le32(&power_regs->hw_power_vddioctrl,
160 POWER_VDDIOCTRL_LINREG_OFFSET_MASK,
161 POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW);
164 static int mxs_get_batt_volt(void)
166 uint32_t volt = readl(&power_regs->hw_power_battmonitor);
168 volt &= POWER_BATTMONITOR_BATT_VAL_MASK;
169 volt >>= POWER_BATTMONITOR_BATT_VAL_OFFSET;
174 static int mxs_is_batt_ready(void)
176 return (mxs_get_batt_volt() >= 3600);
179 static int mxs_is_batt_good(void)
181 uint32_t volt = mxs_get_batt_volt();
183 if ((volt >= 2400) && (volt <= 4300))
186 clrsetbits_le32(&power_regs->hw_power_5vctrl,
187 POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
188 0x3 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
189 writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
190 &power_regs->hw_power_5vctrl_clr);
192 clrsetbits_le32(&power_regs->hw_power_charge,
193 POWER_CHARGE_STOP_ILIMIT_MASK | POWER_CHARGE_BATTCHRG_I_MASK,
194 POWER_CHARGE_STOP_ILIMIT_10MA | 0x3);
196 writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_clr);
197 writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
198 &power_regs->hw_power_5vctrl_clr);
202 volt = mxs_get_batt_volt();
210 writel(POWER_CHARGE_STOP_ILIMIT_MASK | POWER_CHARGE_BATTCHRG_I_MASK,
211 &power_regs->hw_power_charge_clr);
212 writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_set);
217 static void mxs_power_setup_5v_detect(void)
219 /* Start 5V detection */
220 clrsetbits_le32(&power_regs->hw_power_5vctrl,
221 POWER_5VCTRL_VBUSVALID_TRSH_MASK,
222 POWER_5VCTRL_VBUSVALID_TRSH_4V4 |
223 POWER_5VCTRL_PWRUP_VBUS_CMPS);
226 static void mxs_src_power_init(void)
228 /* Improve efficieny and reduce transient ripple */
229 writel(POWER_LOOPCTRL_TOGGLE_DIF | POWER_LOOPCTRL_EN_CM_HYST |
230 POWER_LOOPCTRL_EN_DF_HYST, &power_regs->hw_power_loopctrl_set);
232 clrsetbits_le32(&power_regs->hw_power_dclimits,
233 POWER_DCLIMITS_POSLIMIT_BUCK_MASK,
234 0x30 << POWER_DCLIMITS_POSLIMIT_BUCK_OFFSET);
236 if (!fixed_batt_supply) {
237 /* FIXME: This requires the LRADC to be set up! */
238 setbits_le32(&power_regs->hw_power_battmonitor,
239 POWER_BATTMONITOR_EN_BATADJ);
241 clrbits_le32(&power_regs->hw_power_battmonitor,
242 POWER_BATTMONITOR_EN_BATADJ);
245 /* Increase the RCSCALE level for quick DCDC response to dynamic load */
246 clrsetbits_le32(&power_regs->hw_power_loopctrl,
247 POWER_LOOPCTRL_EN_RCSCALE_MASK,
248 POWER_LOOPCTRL_RCSCALE_THRESH |
249 POWER_LOOPCTRL_EN_RCSCALE_8X);
251 clrsetbits_le32(&power_regs->hw_power_minpwr,
252 POWER_MINPWR_HALFFETS, POWER_MINPWR_DOUBLE_FETS);
254 if (!fixed_batt_supply) {
255 /* 5V to battery handoff ... FIXME */
256 setbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
258 clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
262 static void mxs_power_init_4p2_params(void)
264 /* Setup 4P2 parameters */
265 clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
266 POWER_DCDC4P2_CMPTRIP_MASK | POWER_DCDC4P2_TRG_MASK,
267 POWER_DCDC4P2_TRG_4V2 | (31 << POWER_DCDC4P2_CMPTRIP_OFFSET));
269 clrsetbits_le32(&power_regs->hw_power_5vctrl,
270 POWER_5VCTRL_HEADROOM_ADJ_MASK,
271 0x4 << POWER_5VCTRL_HEADROOM_ADJ_OFFSET);
273 clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
274 POWER_DCDC4P2_DROPOUT_CTRL_MASK,
275 POWER_DCDC4P2_DROPOUT_CTRL_100MV |
276 POWER_DCDC4P2_DROPOUT_CTRL_SRC_SEL);
278 clrsetbits_le32(&power_regs->hw_power_5vctrl,
279 POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
280 0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
283 static void mxs_enable_4p2_dcdc_input(int xfer)
285 uint32_t tmp, vbus_thresh, vbus_5vdetect, pwd_bo;
286 uint32_t prev_5v_brnout, prev_5v_droop;
288 prev_5v_brnout = readl(&power_regs->hw_power_5vctrl) &
289 POWER_5VCTRL_PWDN_5VBRNOUT;
290 prev_5v_droop = readl(&power_regs->hw_power_ctrl) &
291 POWER_CTRL_ENIRQ_VDD5V_DROOP;
293 clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_PWDN_5VBRNOUT);
294 writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
295 &power_regs->hw_power_reset);
297 clrbits_le32(&power_regs->hw_power_ctrl, POWER_CTRL_ENIRQ_VDD5V_DROOP);
299 if (xfer && (readl(&power_regs->hw_power_5vctrl) &
300 POWER_5VCTRL_ENABLE_DCDC)) {
305 * Recording orignal values that will be modified temporarlily
306 * to handle a chip bug. See chip errata for CQ ENGR00115837
308 tmp = readl(&power_regs->hw_power_5vctrl);
309 vbus_thresh = tmp & POWER_5VCTRL_VBUSVALID_TRSH_MASK;
310 vbus_5vdetect = tmp & POWER_5VCTRL_VBUSVALID_5VDETECT;
312 pwd_bo = readl(&power_regs->hw_power_minpwr) & POWER_MINPWR_PWD_BO;
315 * Disable mechanisms that get erroneously tripped by when setting
316 * the DCDC4P2 EN_DCDC
318 clrbits_le32(&power_regs->hw_power_5vctrl,
319 POWER_5VCTRL_VBUSVALID_5VDETECT |
320 POWER_5VCTRL_VBUSVALID_TRSH_MASK);
322 writel(POWER_MINPWR_PWD_BO, &power_regs->hw_power_minpwr_set);
325 setbits_le32(&power_regs->hw_power_5vctrl,
326 POWER_5VCTRL_DCDC_XFER);
328 clrbits_le32(&power_regs->hw_power_5vctrl,
329 POWER_5VCTRL_DCDC_XFER);
331 setbits_le32(&power_regs->hw_power_5vctrl,
332 POWER_5VCTRL_ENABLE_DCDC);
334 setbits_le32(&power_regs->hw_power_dcdc4p2,
335 POWER_DCDC4P2_ENABLE_DCDC);
340 clrsetbits_le32(&power_regs->hw_power_5vctrl,
341 POWER_5VCTRL_VBUSVALID_TRSH_MASK, vbus_thresh);
344 writel(vbus_5vdetect, &power_regs->hw_power_5vctrl_set);
347 clrbits_le32(&power_regs->hw_power_minpwr, POWER_MINPWR_PWD_BO);
349 while (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ)
350 writel(POWER_CTRL_VBUS_VALID_IRQ,
351 &power_regs->hw_power_ctrl_clr);
353 if (prev_5v_brnout) {
354 writel(POWER_5VCTRL_PWDN_5VBRNOUT,
355 &power_regs->hw_power_5vctrl_set);
356 writel(POWER_RESET_UNLOCK_KEY,
357 &power_regs->hw_power_reset);
359 writel(POWER_5VCTRL_PWDN_5VBRNOUT,
360 &power_regs->hw_power_5vctrl_clr);
361 writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
362 &power_regs->hw_power_reset);
365 while (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VDD5V_DROOP_IRQ)
366 writel(POWER_CTRL_VDD5V_DROOP_IRQ,
367 &power_regs->hw_power_ctrl_clr);
370 clrbits_le32(&power_regs->hw_power_ctrl,
371 POWER_CTRL_ENIRQ_VDD5V_DROOP);
373 setbits_le32(&power_regs->hw_power_ctrl,
374 POWER_CTRL_ENIRQ_VDD5V_DROOP);
377 static void mxs_power_init_4p2_regulator(void)
381 setbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_ENABLE_4P2);
383 writel(POWER_CHARGE_ENABLE_LOAD, &power_regs->hw_power_charge_set);
385 writel(POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
386 &power_regs->hw_power_5vctrl_clr);
387 clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_TRG_MASK);
389 /* Power up the 4p2 rail and logic/control */
390 writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
391 &power_regs->hw_power_5vctrl_clr);
394 * Start charging up the 4p2 capacitor. We ramp of this charge
395 * gradually to avoid large inrush current from the 5V cable which can
396 * cause transients/problems
398 mxs_enable_4p2_dcdc_input(0);
400 if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) {
402 * If we arrived here, we were unable to recover from mx23 chip
403 * errata 5837. 4P2 is disabled and sufficient battery power is
404 * not present. Exiting to not enable DCDC power during 5V
407 clrbits_le32(&power_regs->hw_power_dcdc4p2,
408 POWER_DCDC4P2_ENABLE_DCDC);
409 writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
410 &power_regs->hw_power_5vctrl_set);
415 * Here we set the 4p2 brownout level to something very close to 4.2V.
416 * We then check the brownout status. If the brownout status is false,
417 * the voltage is already close to the target voltage of 4.2V so we
418 * can go ahead and set the 4P2 current limit to our max target limit.
419 * If the brownout status is true, we need to ramp us the current limit
420 * so that we don't cause large inrush current issues. We step up the
421 * current limit until the brownout status is false or until we've
422 * reached our maximum defined 4p2 current limit.
424 clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
425 POWER_DCDC4P2_BO_MASK,
426 22 << POWER_DCDC4P2_BO_OFFSET); /* 4.15V */
428 if (!(readl(&power_regs->hw_power_sts) & POWER_STS_DCDC_4P2_BO)) {
429 setbits_le32(&power_regs->hw_power_5vctrl,
430 0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
432 tmp = (readl(&power_regs->hw_power_5vctrl) &
433 POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK) >>
434 POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET;
436 if (!(readl(&power_regs->hw_power_sts) &
437 POWER_STS_DCDC_4P2_BO)) {
438 tmp = readl(&power_regs->hw_power_5vctrl);
439 tmp |= POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK;
441 writel(tmp, &power_regs->hw_power_5vctrl);
445 tmp2 = readl(&power_regs->hw_power_5vctrl);
446 tmp2 &= ~POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK;
448 POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET;
449 writel(tmp2, &power_regs->hw_power_5vctrl);
455 clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_BO_MASK);
456 writel(POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
459 static void mxs_power_init_dcdc_4p2_source(void)
461 if (!(readl(&power_regs->hw_power_dcdc4p2) &
462 POWER_DCDC4P2_ENABLE_DCDC)) {
466 mxs_enable_4p2_dcdc_input(1);
468 if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) {
469 clrbits_le32(&power_regs->hw_power_dcdc4p2,
470 POWER_DCDC4P2_ENABLE_DCDC);
471 writel(POWER_5VCTRL_ENABLE_DCDC,
472 &power_regs->hw_power_5vctrl_clr);
473 writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
474 &power_regs->hw_power_5vctrl_set);
478 static void mxs_power_enable_4p2(void)
480 uint32_t vdddctrl, vddactrl, vddioctrl;
483 vdddctrl = readl(&power_regs->hw_power_vdddctrl);
484 vddactrl = readl(&power_regs->hw_power_vddactrl);
485 vddioctrl = readl(&power_regs->hw_power_vddioctrl);
487 setbits_le32(&power_regs->hw_power_vdddctrl,
488 POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG |
489 POWER_VDDDCTRL_PWDN_BRNOUT);
491 setbits_le32(&power_regs->hw_power_vddactrl,
492 POWER_VDDACTRL_DISABLE_FET | POWER_VDDACTRL_ENABLE_LINREG |
493 POWER_VDDACTRL_PWDN_BRNOUT);
495 setbits_le32(&power_regs->hw_power_vddioctrl,
496 POWER_VDDIOCTRL_DISABLE_FET | POWER_VDDIOCTRL_PWDN_BRNOUT);
498 mxs_power_init_4p2_params();
499 mxs_power_init_4p2_regulator();
501 /* Shutdown battery (none present) */
502 if (!mxs_is_batt_ready()) {
503 clrbits_le32(&power_regs->hw_power_dcdc4p2,
504 POWER_DCDC4P2_BO_MASK);
505 writel(POWER_CTRL_DCDC4P2_BO_IRQ,
506 &power_regs->hw_power_ctrl_clr);
507 writel(POWER_CTRL_ENIRQ_DCDC4P2_BO,
508 &power_regs->hw_power_ctrl_clr);
511 mxs_power_init_dcdc_4p2_source();
513 writel(vdddctrl, &power_regs->hw_power_vdddctrl);
515 writel(vddactrl, &power_regs->hw_power_vddactrl);
517 writel(vddioctrl, &power_regs->hw_power_vddioctrl);
520 * Check if FET is enabled on either powerout and if so,
524 tmp |= !(readl(&power_regs->hw_power_vdddctrl) &
525 POWER_VDDDCTRL_DISABLE_FET);
526 tmp |= !(readl(&power_regs->hw_power_vddactrl) &
527 POWER_VDDACTRL_DISABLE_FET);
528 tmp |= !(readl(&power_regs->hw_power_vddioctrl) &
529 POWER_VDDIOCTRL_DISABLE_FET);
531 writel(POWER_CHARGE_ENABLE_LOAD,
532 &power_regs->hw_power_charge_clr);
535 static void mxs_boot_valid_5v(void)
538 * Use VBUSVALID level instead of VDD5V_GT_VDDIO level to trigger a 5V
539 * disconnect event. FIXME
541 writel(POWER_5VCTRL_VBUSVALID_5VDETECT,
542 &power_regs->hw_power_5vctrl_set);
544 /* Configure polarity to check for 5V disconnection. */
545 writel(POWER_CTRL_POLARITY_VBUSVALID |
546 POWER_CTRL_POLARITY_VDD5V_GT_VDDIO,
547 &power_regs->hw_power_ctrl_clr);
549 writel(POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_VDD5V_GT_VDDIO_IRQ,
550 &power_regs->hw_power_ctrl_clr);
552 mxs_power_enable_4p2();
555 static void mxs_powerdown(void)
557 writel(POWER_RESET_UNLOCK_KEY, &power_regs->hw_power_reset);
558 writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
559 &power_regs->hw_power_reset);
562 static void mxs_batt_boot(void)
564 clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_PWDN_5VBRNOUT);
565 clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_ENABLE_DCDC);
567 clrbits_le32(&power_regs->hw_power_dcdc4p2,
568 POWER_DCDC4P2_ENABLE_DCDC | POWER_DCDC4P2_ENABLE_4P2);
569 writel(POWER_CHARGE_ENABLE_LOAD, &power_regs->hw_power_charge_clr);
571 /* 5V to battery handoff. */
572 setbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
574 clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
576 writel(POWER_CTRL_ENIRQ_DCDC4P2_BO, &power_regs->hw_power_ctrl_clr);
578 clrsetbits_le32(&power_regs->hw_power_minpwr,
579 POWER_MINPWR_HALFFETS, POWER_MINPWR_DOUBLE_FETS);
581 mxs_power_set_linreg();
583 clrbits_le32(&power_regs->hw_power_vdddctrl,
584 POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG);
586 clrbits_le32(&power_regs->hw_power_vddactrl,
587 POWER_VDDACTRL_DISABLE_FET | POWER_VDDACTRL_ENABLE_LINREG);
589 clrbits_le32(&power_regs->hw_power_vddioctrl,
590 POWER_VDDIOCTRL_DISABLE_FET);
592 setbits_le32(&power_regs->hw_power_5vctrl,
593 POWER_5VCTRL_PWD_CHARGE_4P2_MASK);
595 setbits_le32(&power_regs->hw_power_5vctrl,
596 POWER_5VCTRL_ENABLE_DCDC);
598 clrsetbits_le32(&power_regs->hw_power_5vctrl,
599 POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
600 0x8 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
603 static void mxs_handle_5v_conflict(void)
607 setbits_le32(&power_regs->hw_power_vddioctrl,
608 POWER_VDDIOCTRL_BO_OFFSET_MASK);
611 tmp = readl(&power_regs->hw_power_sts);
613 if (tmp & POWER_STS_VDDIO_BO) {
615 * VDDIO has a brownout, then the VDD5V_GT_VDDIO becomes
622 if (tmp & POWER_STS_VDD5V_GT_VDDIO) {
630 if (tmp & POWER_STS_PSWITCH_MASK) {
637 static void mxs_5v_boot(void)
640 * NOTE: In original IMX-Bootlets, this also checks for VBUSVALID,
641 * but their implementation always returns 1 so we omit it here.
643 if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
649 if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
654 mxs_handle_5v_conflict();
657 static void mxs_fixed_batt_boot(void)
659 writel(POWER_CTRL_ENIRQ_BATT_BO, &power_regs->hw_power_ctrl_clr);
661 setbits_le32(&power_regs->hw_power_5vctrl,
662 POWER_5VCTRL_PWDN_5VBRNOUT |
663 POWER_5VCTRL_ENABLE_DCDC |
664 POWER_5VCTRL_ILIMIT_EQ_ZERO |
665 POWER_5VCTRL_PWDN_5VBRNOUT |
666 POWER_5VCTRL_PWD_CHARGE_4P2_MASK);
668 writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_set);
670 clrbits_le32(&power_regs->hw_power_vdddctrl,
671 POWER_VDDDCTRL_DISABLE_FET |
672 POWER_VDDDCTRL_ENABLE_LINREG |
673 POWER_VDDDCTRL_DISABLE_STEPPING);
675 clrbits_le32(&power_regs->hw_power_vddactrl,
676 POWER_VDDACTRL_DISABLE_FET | POWER_VDDACTRL_ENABLE_LINREG |
677 POWER_VDDACTRL_DISABLE_STEPPING);
679 clrbits_le32(&power_regs->hw_power_vddioctrl,
680 POWER_VDDIOCTRL_DISABLE_FET |
681 POWER_VDDIOCTRL_DISABLE_STEPPING);
683 /* Stop 5V detection */
684 writel(POWER_5VCTRL_PWRUP_VBUS_CMPS,
685 &power_regs->hw_power_5vctrl_clr);
688 static void mxs_init_batt_bo(void)
690 clrsetbits_le32(&power_regs->hw_power_battmonitor,
691 POWER_BATTMONITOR_BRWNOUT_LVL_MASK,
692 BATT_BO_VAL << POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET);
694 writel(POWER_CTRL_BATT_BO_IRQ, &power_regs->hw_power_ctrl_clr);
695 writel(POWER_CTRL_ENIRQ_BATT_BO, &power_regs->hw_power_ctrl_clr);
698 static void mxs_switch_vddd_to_dcdc_source(void)
700 clrsetbits_le32(&power_regs->hw_power_vdddctrl,
701 POWER_VDDDCTRL_LINREG_OFFSET_MASK,
702 POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW);
704 clrbits_le32(&power_regs->hw_power_vdddctrl,
705 POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG |
706 POWER_VDDDCTRL_DISABLE_STEPPING);
709 static void mxs_power_configure_power_source(void)
711 struct mxs_lradc_regs *lradc_regs =
712 (struct mxs_lradc_regs *)MXS_LRADC_BASE;
714 mxs_src_power_init();
716 if (!fixed_batt_supply) {
717 if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
718 if (mxs_is_batt_ready()) {
719 /* 5V source detected, good battery detected. */
722 if (!mxs_is_batt_good()) {
723 /* 5V source detected, bad battery detected. */
724 writel(LRADC_CONVERSION_AUTOMATIC,
725 &lradc_regs->hw_lradc_conversion_clr);
726 clrbits_le32(&power_regs->hw_power_battmonitor,
727 POWER_BATTMONITOR_BATT_VAL_MASK);
732 /* 5V not detected, booting from battery. */
736 mxs_fixed_batt_boot();
739 mxs_power_clock2pll();
743 mxs_switch_vddd_to_dcdc_source();
746 static void mxs_enable_output_rail_protection(void)
748 writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
749 POWER_CTRL_VDDIO_BO_IRQ, &power_regs->hw_power_ctrl_clr);
751 setbits_le32(&power_regs->hw_power_vdddctrl,
752 POWER_VDDDCTRL_PWDN_BRNOUT);
754 setbits_le32(&power_regs->hw_power_vddactrl,
755 POWER_VDDACTRL_PWDN_BRNOUT);
757 setbits_le32(&power_regs->hw_power_vddioctrl,
758 POWER_VDDIOCTRL_PWDN_BRNOUT);
761 static int mxs_get_vddio_power_source_off(void)
765 if ((readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) &&
766 !(readl(&power_regs->hw_power_5vctrl) &
767 POWER_5VCTRL_ILIMIT_EQ_ZERO)) {
769 tmp = readl(&power_regs->hw_power_vddioctrl);
770 if (tmp & POWER_VDDIOCTRL_DISABLE_FET) {
771 if ((tmp & POWER_VDDIOCTRL_LINREG_OFFSET_MASK) ==
772 POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS) {
777 if (!(readl(&power_regs->hw_power_5vctrl) &
778 POWER_5VCTRL_ENABLE_DCDC)) {
779 if ((tmp & POWER_VDDIOCTRL_LINREG_OFFSET_MASK) ==
780 POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS) {
789 static int mxs_get_vddd_power_source_off(void)
793 tmp = readl(&power_regs->hw_power_vdddctrl);
794 if (tmp & POWER_VDDDCTRL_DISABLE_FET) {
795 if ((tmp & POWER_VDDDCTRL_LINREG_OFFSET_MASK) ==
796 POWER_VDDDCTRL_LINREG_OFFSET_0STEPS) {
801 if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
802 if (!(readl(&power_regs->hw_power_5vctrl) &
803 POWER_5VCTRL_ENABLE_DCDC)) {
808 if (!(tmp & POWER_VDDDCTRL_ENABLE_LINREG)) {
809 if ((tmp & POWER_VDDDCTRL_LINREG_OFFSET_MASK) ==
810 POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW) {
818 static int mxs_get_vdda_power_source_off(void)
822 tmp = readl(&power_regs->hw_power_vddactrl);
823 if (tmp & POWER_VDDACTRL_DISABLE_FET) {
824 if ((tmp & POWER_VDDACTRL_LINREG_OFFSET_MASK) ==
825 POWER_VDDACTRL_LINREG_OFFSET_0STEPS) {
830 if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
831 if (!(readl(&power_regs->hw_power_5vctrl) &
832 POWER_5VCTRL_ENABLE_DCDC)) {
837 if (!(tmp & POWER_VDDACTRL_ENABLE_LINREG)) {
838 if ((tmp & POWER_VDDACTRL_LINREG_OFFSET_MASK) ==
839 POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW) {
847 struct mxs_vddx_cfg {
852 int (*powered_by_linreg)(void);
856 uint32_t bo_offset_mask;
857 uint32_t bo_offset_offset;
860 static const struct mxs_vddx_cfg mxs_vddio_cfg = {
861 .reg = &(((struct mxs_power_regs *)MXS_POWER_BASE)->
866 .powered_by_linreg = mxs_get_vddio_power_source_off,
867 .trg_mask = POWER_VDDIOCTRL_TRG_MASK,
868 .bo_irq = POWER_CTRL_VDDIO_BO_IRQ,
869 .bo_enirq = POWER_CTRL_ENIRQ_VDDIO_BO,
870 .bo_offset_mask = POWER_VDDIOCTRL_BO_OFFSET_MASK,
871 .bo_offset_offset = POWER_VDDIOCTRL_BO_OFFSET_OFFSET,
874 static const struct mxs_vddx_cfg mxs_vddd_cfg = {
875 .reg = &(((struct mxs_power_regs *)MXS_POWER_BASE)->
880 .powered_by_linreg = mxs_get_vddd_power_source_off,
881 .trg_mask = POWER_VDDDCTRL_TRG_MASK,
882 .bo_irq = POWER_CTRL_VDDD_BO_IRQ,
883 .bo_enirq = POWER_CTRL_ENIRQ_VDDD_BO,
884 .bo_offset_mask = POWER_VDDDCTRL_BO_OFFSET_MASK,
885 .bo_offset_offset = POWER_VDDDCTRL_BO_OFFSET_OFFSET,
888 static const struct mxs_vddx_cfg mxs_vdda_cfg = {
889 .reg = &(((struct mxs_power_regs *)MXS_POWER_BASE)->
894 .powered_by_linreg = mxs_get_vdda_power_source_off,
895 .trg_mask = POWER_VDDACTRL_TRG_MASK,
896 .bo_irq = POWER_CTRL_VDDA_BO_IRQ,
897 .bo_enirq = POWER_CTRL_ENIRQ_VDDA_BO,
898 .bo_offset_mask = POWER_VDDACTRL_BO_OFFSET_MASK,
899 .bo_offset_offset = POWER_VDDACTRL_BO_OFFSET_OFFSET,
902 static const struct mxs_vddx_cfg mxs_vddmem_cfg = {
903 .reg = &(((struct mxs_power_regs *)MXS_POWER_BASE)->
904 hw_power_vddmemctrl),
908 .bo_offset_mask = POWER_VDDMEMCTRL_BO_OFFSET_MASK,
909 .bo_offset_offset = POWER_VDDMEMCTRL_BO_OFFSET_OFFSET,
912 static void mxs_power_set_vddx(const struct mxs_vddx_cfg *cfg,
913 uint32_t new_target, uint32_t new_brownout)
915 uint32_t cur_target, diff, bo_int = 0;
916 int powered_by_linreg = 0;
919 if (new_target < cfg->lowest_mV)
920 new_target = cfg->lowest_mV;
921 if (new_target > cfg->highest_mV)
922 new_target = cfg->highest_mV;
924 new_brownout = DIV_ROUND(new_target - new_brownout, cfg->step_mV);
926 cur_target = readl(cfg->reg);
927 cur_target &= cfg->trg_mask;
928 cur_target *= cfg->step_mV;
929 cur_target += cfg->lowest_mV;
931 adjust_up = new_target > cur_target;
932 if (cfg->powered_by_linreg)
933 powered_by_linreg = cfg->powered_by_linreg();
936 if (powered_by_linreg) {
937 bo_int = readl(cfg->reg);
938 clrbits_le32(cfg->reg, cfg->bo_enirq);
940 setbits_le32(cfg->reg, cfg->bo_offset_mask);
944 if (abs(new_target - cur_target) > 100) {
946 diff = cur_target + 100;
948 diff = cur_target - 100;
953 diff -= cfg->lowest_mV;
954 diff /= cfg->step_mV;
956 clrsetbits_le32(cfg->reg, cfg->trg_mask, diff);
958 if (powered_by_linreg ||
959 (readl(&power_regs->hw_power_sts) &
960 POWER_STS_VDD5V_GT_VDDIO)) {
963 while (!(readl(&power_regs->hw_power_sts) &
969 cur_target = readl(cfg->reg);
970 cur_target &= cfg->trg_mask;
971 cur_target *= cfg->step_mV;
972 cur_target += cfg->lowest_mV;
973 } while (new_target > cur_target);
975 if (adjust_up && powered_by_linreg) {
976 writel(cfg->bo_irq, &power_regs->hw_power_ctrl_clr);
977 if (bo_int & cfg->bo_enirq)
978 setbits_le32(cfg->reg, cfg->bo_enirq);
981 clrsetbits_le32(cfg->reg, cfg->bo_offset_mask,
982 new_brownout << cfg->bo_offset_offset);
985 static void mxs_setup_batt_detect(void)
988 mxs_lradc_enable_batt_measurement();
992 void mxs_power_init(void)
994 mxs_power_clock2xtal();
995 mxs_power_clear_auto_restart();
996 mxs_power_set_linreg();
998 if (!fixed_batt_supply) {
999 mxs_power_setup_5v_detect();
1000 mxs_setup_batt_detect();
1003 mxs_power_configure_power_source();
1004 mxs_enable_output_rail_protection();
1006 mxs_power_set_vddx(&mxs_vddio_cfg, VDDIO_VAL, VDDIO_BO_VAL);
1007 mxs_power_set_vddx(&mxs_vddd_cfg, VDDD_VAL, VDDD_BO_VAL);
1008 mxs_power_set_vddx(&mxs_vdda_cfg, VDDA_VAL, VDDA_BO_VAL);
1010 mxs_power_set_vddx(&mxs_vddmem_cfg, VDDMEM_VAL, VDDMEM_BO_VAL);
1012 setbits_le32(&power_regs->hw_power_vddmemctrl,
1013 POWER_VDDMEMCTRL_ENABLE_LINREG);
1015 clrbits_le32(&power_regs->hw_power_vddmemctrl,
1016 POWER_VDDMEMCTRL_ENABLE_ILIMIT);
1018 clrbits_le32(&power_regs->hw_power_vddmemctrl,
1019 POWER_VDDMEMCTRL_ENABLE_LINREG);
1021 writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
1022 POWER_CTRL_VDDIO_BO_IRQ | POWER_CTRL_VDD5V_DROOP_IRQ |
1023 POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_BATT_BO_IRQ |
1024 POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
1025 if (!fixed_batt_supply)
1026 writel(POWER_5VCTRL_PWDN_5VBRNOUT,
1027 &power_regs->hw_power_5vctrl_set);
1030 #ifdef CONFIG_SPL_MX28_PSWITCH_WAIT
1031 void mxs_power_wait_pswitch(void)
1033 while (!(readl(&power_regs->hw_power_sts) & POWER_STS_PSWITCH_MASK))