arch/arm/cpu/arm926ejs/spear/spear600.c

   1 /*
   2  * (C) Copyright 2000-2009
   3  * Viresh Kumar, ST Microelectronics, viresh.kumar@st.com
   4  * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <asm/hardware.h>
  11 #include <asm/io.h>
  12 #include <asm/arch/spr_misc.h>
  13 #include <asm/arch/spr_defs.h>
  14
  15 void spear_late_init(void)
  16 {
  17         struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
  18
  19         writel(0x80000007, &misc_p->arb_icm_ml1);
  20         writel(0x80000007, &misc_p->arb_icm_ml2);
  21         writel(0x80000007, &misc_p->arb_icm_ml3);
  22         writel(0x80000007, &misc_p->arb_icm_ml4);
  23         writel(0x80000007, &misc_p->arb_icm_ml5);
  24         writel(0x80000007, &misc_p->arb_icm_ml6);
  25         writel(0x80000007, &misc_p->arb_icm_ml7);
  26         writel(0x80000007, &misc_p->arb_icm_ml8);
  27         writel(0x80000007, &misc_p->arb_icm_ml9);
  28 }
  29
  30 static void sel_1v8(void)
  31 {
  32         struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
  33         u32 ddr1v8, ddr2v5;
  34
  35         ddr2v5 = readl(&misc_p->ddr_2v5_compensation);
  36         ddr2v5 &= 0x8080ffc0;
  37         ddr2v5 |= 0x78000003;
  38         writel(ddr2v5, &misc_p->ddr_2v5_compensation);
  39
  40         ddr1v8 = readl(&misc_p->ddr_1v8_compensation);
  41         ddr1v8 &= 0x8080ffc0;
  42         ddr1v8 |= 0x78000010;
  43         writel(ddr1v8, &misc_p->ddr_1v8_compensation);
  44
  45         while (!(readl(&misc_p->ddr_1v8_compensation) & DDR_COMP_ACCURATE))
  46                 ;
  47 }
  48
  49 static void sel_2v5(void)
  50 {
  51         struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
  52         u32 ddr1v8, ddr2v5;
  53
  54         ddr1v8 = readl(&misc_p->ddr_1v8_compensation);
  55         ddr1v8 &= 0x8080ffc0;
  56         ddr1v8 |= 0x78000003;
  57         writel(ddr1v8, &misc_p->ddr_1v8_compensation);
  58
  59         ddr2v5 = readl(&misc_p->ddr_2v5_compensation);
  60         ddr2v5 &= 0x8080ffc0;
  61         ddr2v5 |= 0x78000010;
  62         writel(ddr2v5, &misc_p->ddr_2v5_compensation);
  63
  64         while (!(readl(&misc_p->ddr_2v5_compensation) & DDR_COMP_ACCURATE))
  65                 ;
  66 }
  67
  68 /*
  69  * plat_ddr_init:
  70  */
  71 void plat_ddr_init(void)
  72 {
  73         struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
  74         u32 ddrpad;
  75         u32 core3v3, ddr1v8, ddr2v5;
  76
  77         /* DDR pad register configurations */
  78         ddrpad = readl(&misc_p->ddr_pad);
  79         ddrpad &= ~DDR_PAD_CNF_MSK;
  80
  81 #if (CONFIG_DDR_HCLK)
  82         ddrpad |= 0xEAAB;
  83 #elif (CONFIG_DDR_2HCLK)
  84         ddrpad |= 0xEAAD;
  85 #elif (CONFIG_DDR_PLL2)
  86         ddrpad |= 0xEAAD;
  87 #endif
  88         writel(ddrpad, &misc_p->ddr_pad);
  89
  90         /* Compensation register configurations */
  91         core3v3 = readl(&misc_p->core_3v3_compensation);
  92         core3v3 &= 0x8080ffe0;
  93         core3v3 |= 0x78000002;
  94         writel(core3v3, &misc_p->core_3v3_compensation);
  95
  96         ddr1v8 = readl(&misc_p->ddr_1v8_compensation);
  97         ddr1v8 &= 0x8080ffc0;
  98         ddr1v8 |= 0x78000004;
  99         writel(ddr1v8, &misc_p->ddr_1v8_compensation);
 100
 101         ddr2v5 = readl(&misc_p->ddr_2v5_compensation);
 102         ddr2v5 &= 0x8080ffc0;
 103         ddr2v5 |= 0x78000004;
 104         writel(ddr2v5, &misc_p->ddr_2v5_compensation);
 105
 106         if ((readl(&misc_p->ddr_pad) & DDR_PAD_SW_CONF) == DDR_PAD_SW_CONF) {
 107                 /* Software memory configuration */
 108                 if (readl(&misc_p->ddr_pad) & DDR_PAD_SSTL_SEL)
 109                         sel_1v8();
 110                 else
 111                         sel_2v5();
 112         } else {
 113                 /* Hardware memory configuration */
 114                 if (readl(&misc_p->ddr_pad) & DDR_PAD_DRAM_TYPE)
 115                         sel_1v8();
 116                 else
 117                         sel_2v5();
 118         }
 119 }
 120
 121 /*
 122  * xxx_boot_selected:
 123  *
 124  * return true if the particular booting option is selected
 125  * return false otherwise
 126  */
 127 static u32 read_bootstrap(void)
 128 {
 129         return (readl(CONFIG_SPEAR_BOOTSTRAPCFG) >> CONFIG_SPEAR_BOOTSTRAPSHFT)
 130                 & CONFIG_SPEAR_BOOTSTRAPMASK;
 131 }
 132
 133 int snor_boot_selected(void)
 134 {
 135         u32 bootstrap = read_bootstrap();
 136
 137         if (SNOR_BOOT_SUPPORTED) {
 138                 /* Check whether SNOR boot is selected */
 139                 if ((bootstrap & CONFIG_SPEAR_ONLYSNORBOOT) ==
 140                         CONFIG_SPEAR_ONLYSNORBOOT)
 141                         return true;
 142
 143                 if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
 144                         CONFIG_SPEAR_NORNAND8BOOT)
 145                         return true;
 146
 147                 if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
 148                         CONFIG_SPEAR_NORNAND16BOOT)
 149                         return true;
 150         }
 151
 152         return false;
 153 }
 154
 155 int nand_boot_selected(void)
 156 {
 157         u32 bootstrap = read_bootstrap();
 158
 159         if (NAND_BOOT_SUPPORTED) {
 160                 /* Check whether NAND boot is selected */
 161                 if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
 162                         CONFIG_SPEAR_NORNAND8BOOT)
 163                         return true;
 164
 165                 if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
 166                         CONFIG_SPEAR_NORNAND16BOOT)
 167                         return true;
 168         }
 169
 170         return false;
 171 }
 172
 173 int pnor_boot_selected(void)
 174 {
 175         /* Parallel NOR boot is not selected in any SPEAr600 revision */
 176         return false;
 177 }
 178
 179 int usb_boot_selected(void)
 180 {
 181         u32 bootstrap = read_bootstrap();
 182
 183         if (USB_BOOT_SUPPORTED) {
 184                 /* Check whether USB boot is selected */
 185                 if (!(bootstrap & CONFIG_SPEAR_USBBOOT))
 186                         return true;
 187         }
 188
 189         return false;
 190 }
 191
 192 int tftp_boot_selected(void)
 193 {
 194         /* TFTP boot is not selected in any SPEAr600 revision */
 195         return false;
 196 }
 197
 198 int uart_boot_selected(void)
 199 {
 200         /* UART boot is not selected in any SPEAr600 revision */
 201         return false;
 202 }
 203
 204 int spi_boot_selected(void)
 205 {
 206         /* SPI boot is not selected in any SPEAr600 revision */
 207         return false;
 208 }
 209
 210 int i2c_boot_selected(void)
 211 {
 212         /* I2C boot is not selected in any SPEAr600 revision */
 213         return false;
 214 }
 215
 216 int mmc_boot_selected(void)
 217 {
 218         return false;
 219 }
 220
 221 void plat_late_init(void)
 222 {
 223         spear_late_init();
 224 }