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Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'
[karo-tx-uboot.git] / arch / arm / cpu / arm926ejs / spear / spear600.c
1 /*
2  * (C) Copyright 2000-2009
3  * Viresh Kumar, ST Microelectronics, viresh.kumar@st.com
4  * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com
5  *
6  * See file CREDITS for list of people who contributed to this
7  * project.
8  *
9  * This program is free software; you can redistribute it and/or
10  * modify it under the terms of the GNU General Public License as
11  * published by the Free Software Foundation; either version 2 of
12  * the License, or (at your option) any later version.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  * GNU General Public License for more details.
18  *
19  * You should have received a copy of the GNU General Public License
20  * along with this program; if not, write to the Free Software
21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22  * MA 02111-1307 USA
23  */
24
25 #include <common.h>
26 #include <asm/hardware.h>
27 #include <asm/io.h>
28 #include <asm/arch/spr_misc.h>
29 #include <asm/arch/spr_defs.h>
30
31 static void sel_1v8(void)
32 {
33         struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
34         u32 ddr1v8, ddr2v5;
35
36         ddr2v5 = readl(&misc_p->ddr_2v5_compensation);
37         ddr2v5 &= 0x8080ffc0;
38         ddr2v5 |= 0x78000003;
39         writel(ddr2v5, &misc_p->ddr_2v5_compensation);
40
41         ddr1v8 = readl(&misc_p->ddr_1v8_compensation);
42         ddr1v8 &= 0x8080ffc0;
43         ddr1v8 |= 0x78000010;
44         writel(ddr1v8, &misc_p->ddr_1v8_compensation);
45
46         while (!(readl(&misc_p->ddr_1v8_compensation) & DDR_COMP_ACCURATE))
47                 ;
48 }
49
50 static void sel_2v5(void)
51 {
52         struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
53         u32 ddr1v8, ddr2v5;
54
55         ddr1v8 = readl(&misc_p->ddr_1v8_compensation);
56         ddr1v8 &= 0x8080ffc0;
57         ddr1v8 |= 0x78000003;
58         writel(ddr1v8, &misc_p->ddr_1v8_compensation);
59
60         ddr2v5 = readl(&misc_p->ddr_2v5_compensation);
61         ddr2v5 &= 0x8080ffc0;
62         ddr2v5 |= 0x78000010;
63         writel(ddr2v5, &misc_p->ddr_2v5_compensation);
64
65         while (!(readl(&misc_p->ddr_2v5_compensation) & DDR_COMP_ACCURATE))
66                 ;
67 }
68
69 /*
70  * plat_ddr_init:
71  */
72 void plat_ddr_init(void)
73 {
74         struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
75         u32 ddrpad;
76         u32 core3v3, ddr1v8, ddr2v5;
77
78         /* DDR pad register configurations */
79         ddrpad = readl(&misc_p->ddr_pad);
80         ddrpad &= ~DDR_PAD_CNF_MSK;
81
82 #if (CONFIG_DDR_HCLK)
83         ddrpad |= 0xEAAB;
84 #elif (CONFIG_DDR_2HCLK)
85         ddrpad |= 0xEAAD;
86 #elif (CONFIG_DDR_PLL2)
87         ddrpad |= 0xEAAD;
88 #endif
89         writel(ddrpad, &misc_p->ddr_pad);
90
91         /* Compensation register configurations */
92         core3v3 = readl(&misc_p->core_3v3_compensation);
93         core3v3 &= 0x8080ffe0;
94         core3v3 |= 0x78000002;
95         writel(core3v3, &misc_p->core_3v3_compensation);
96
97         ddr1v8 = readl(&misc_p->ddr_1v8_compensation);
98         ddr1v8 &= 0x8080ffc0;
99         ddr1v8 |= 0x78000004;
100         writel(ddr1v8, &misc_p->ddr_1v8_compensation);
101
102         ddr2v5 = readl(&misc_p->ddr_2v5_compensation);
103         ddr2v5 &= 0x8080ffc0;
104         ddr2v5 |= 0x78000004;
105         writel(ddr2v5, &misc_p->ddr_2v5_compensation);
106
107         if ((readl(&misc_p->ddr_pad) & DDR_PAD_SW_CONF) == DDR_PAD_SW_CONF) {
108                 /* Software memory configuration */
109                 if (readl(&misc_p->ddr_pad) & DDR_PAD_SSTL_SEL)
110                         sel_1v8();
111                 else
112                         sel_2v5();
113         } else {
114                 /* Hardware memory configuration */
115                 if (readl(&misc_p->ddr_pad) & DDR_PAD_DRAM_TYPE)
116                         sel_1v8();
117                 else
118                         sel_2v5();
119         }
120 }
121
122 /*
123  * soc_init:
124  */
125 void soc_init(void)
126 {
127         /* Nothing to be done for SPEAr600 */
128 }
129
130 /*
131  * xxx_boot_selected:
132  *
133  * return true if the particular booting option is selected
134  * return false otherwise
135  */
136 static u32 read_bootstrap(void)
137 {
138         return (readl(CONFIG_SPEAR_BOOTSTRAPCFG) >> CONFIG_SPEAR_BOOTSTRAPSHFT)
139                 & CONFIG_SPEAR_BOOTSTRAPMASK;
140 }
141
142 int snor_boot_selected(void)
143 {
144         u32 bootstrap = read_bootstrap();
145
146         if (SNOR_BOOT_SUPPORTED) {
147                 /* Check whether SNOR boot is selected */
148                 if ((bootstrap & CONFIG_SPEAR_ONLYSNORBOOT) ==
149                         CONFIG_SPEAR_ONLYSNORBOOT)
150                         return true;
151
152                 if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
153                         CONFIG_SPEAR_NORNAND8BOOT)
154                         return true;
155
156                 if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
157                         CONFIG_SPEAR_NORNAND16BOOT)
158                         return true;
159         }
160
161         return false;
162 }
163
164 int nand_boot_selected(void)
165 {
166         u32 bootstrap = read_bootstrap();
167
168         if (NAND_BOOT_SUPPORTED) {
169                 /* Check whether NAND boot is selected */
170                 if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
171                         CONFIG_SPEAR_NORNAND8BOOT)
172                         return true;
173
174                 if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
175                         CONFIG_SPEAR_NORNAND16BOOT)
176                         return true;
177         }
178
179         return false;
180 }
181
182 int pnor_boot_selected(void)
183 {
184         /* Parallel NOR boot is not selected in any SPEAr600 revision */
185         return false;
186 }
187
188 int usb_boot_selected(void)
189 {
190         u32 bootstrap = read_bootstrap();
191
192         if (USB_BOOT_SUPPORTED) {
193                 /* Check whether USB boot is selected */
194                 if (!(bootstrap & CONFIG_SPEAR_USBBOOT))
195                         return true;
196         }
197
198         return false;
199 }
200
201 int tftp_boot_selected(void)
202 {
203         /* TFTP boot is not selected in any SPEAr600 revision */
204         return false;
205 }
206
207 int uart_boot_selected(void)
208 {
209         /* UART boot is not selected in any SPEAr600 revision */
210         return false;
211 }
212
213 int spi_boot_selected(void)
214 {
215         /* SPI boot is not selected in any SPEAr600 revision */
216         return false;
217 }
218
219 int i2c_boot_selected(void)
220 {
221         /* I2C boot is not selected in any SPEAr600 revision */
222         return false;
223 }
224
225 int mmc_boot_selected(void)
226 {
227         return false;
228 }
229
230 void plat_late_init(void)
231 {
232         spear_late_init();
233 }