arch/arm/cpu/arm926ejs/spear/spear600.c

   1 /*
   2  * (C) Copyright 2000-2009
   3  * Viresh Kumar, ST Microelectronics, viresh.kumar@st.com
   4  * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <common.h>
  26 #include <asm/hardware.h>
  27 #include <asm/io.h>
  28 #include <asm/arch/spr_misc.h>
  29 #include <asm/arch/spr_defs.h>
  30
  31 #define FALSE                           0
  32 #define TRUE                            (!FALSE)
  33
  34 static void sel_1v8(void)
  35 {
  36         struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
  37         u32 ddr1v8, ddr2v5;
  38
  39         ddr2v5 = readl(&misc_p->ddr_2v5_compensation);
  40         ddr2v5 &= 0x8080ffc0;
  41         ddr2v5 |= 0x78000003;
  42         writel(ddr2v5, &misc_p->ddr_2v5_compensation);
  43
  44         ddr1v8 = readl(&misc_p->ddr_1v8_compensation);
  45         ddr1v8 &= 0x8080ffc0;
  46         ddr1v8 |= 0x78000010;
  47         writel(ddr1v8, &misc_p->ddr_1v8_compensation);
  48
  49         while (!(readl(&misc_p->ddr_1v8_compensation) & DDR_COMP_ACCURATE))
  50                 ;
  51 }
  52
  53 static void sel_2v5(void)
  54 {
  55         struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
  56         u32 ddr1v8, ddr2v5;
  57
  58         ddr1v8 = readl(&misc_p->ddr_1v8_compensation);
  59         ddr1v8 &= 0x8080ffc0;
  60         ddr1v8 |= 0x78000003;
  61         writel(ddr1v8, &misc_p->ddr_1v8_compensation);
  62
  63         ddr2v5 = readl(&misc_p->ddr_2v5_compensation);
  64         ddr2v5 &= 0x8080ffc0;
  65         ddr2v5 |= 0x78000010;
  66         writel(ddr2v5, &misc_p->ddr_2v5_compensation);
  67
  68         while (!(readl(&misc_p->ddr_2v5_compensation) & DDR_COMP_ACCURATE))
  69                 ;
  70 }
  71
  72 /*
  73  * plat_ddr_init:
  74  */
  75 void plat_ddr_init(void)
  76 {
  77         struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
  78         u32 ddrpad;
  79         u32 core3v3, ddr1v8, ddr2v5;
  80
  81         /* DDR pad register configurations */
  82         ddrpad = readl(&misc_p->ddr_pad);
  83         ddrpad &= ~DDR_PAD_CNF_MSK;
  84
  85 #if (CONFIG_DDR_HCLK)
  86         ddrpad |= 0xEAAB;
  87 #elif (CONFIG_DDR_2HCLK)
  88         ddrpad |= 0xEAAD;
  89 #elif (CONFIG_DDR_PLL2)
  90         ddrpad |= 0xEAAD;
  91 #endif
  92         writel(ddrpad, &misc_p->ddr_pad);
  93
  94         /* Compensation register configurations */
  95         core3v3 = readl(&misc_p->core_3v3_compensation);
  96         core3v3 &= 0x8080ffe0;
  97         core3v3 |= 0x78000002;
  98         writel(core3v3, &misc_p->core_3v3_compensation);
  99
 100         ddr1v8 = readl(&misc_p->ddr_1v8_compensation);
 101         ddr1v8 &= 0x8080ffc0;
 102         ddr1v8 |= 0x78000004;
 103         writel(ddr1v8, &misc_p->ddr_1v8_compensation);
 104
 105         ddr2v5 = readl(&misc_p->ddr_2v5_compensation);
 106         ddr2v5 &= 0x8080ffc0;
 107         ddr2v5 |= 0x78000004;
 108         writel(ddr2v5, &misc_p->ddr_2v5_compensation);
 109
 110         if ((readl(&misc_p->ddr_pad) & DDR_PAD_SW_CONF) == DDR_PAD_SW_CONF) {
 111                 /* Software memory configuration */
 112                 if (readl(&misc_p->ddr_pad) & DDR_PAD_SSTL_SEL)
 113                         sel_1v8();
 114                 else
 115                         sel_2v5();
 116         } else {
 117                 /* Hardware memory configuration */
 118                 if (readl(&misc_p->ddr_pad) & DDR_PAD_DRAM_TYPE)
 119                         sel_1v8();
 120                 else
 121                         sel_2v5();
 122         }
 123 }
 124
 125 /*
 126  * soc_init:
 127  */
 128 void soc_init(void)
 129 {
 130         /* Nothing to be done for SPEAr600 */
 131 }
 132
 133 /*
 134  * xxx_boot_selected:
 135  *
 136  * return TRUE if the particular booting option is selected
 137  * return FALSE otherwise
 138  */
 139 static u32 read_bootstrap(void)
 140 {
 141         return (readl(CONFIG_SPEAR_BOOTSTRAPCFG) >> CONFIG_SPEAR_BOOTSTRAPSHFT)
 142                 & CONFIG_SPEAR_BOOTSTRAPMASK;
 143 }
 144
 145 int snor_boot_selected(void)
 146 {
 147         u32 bootstrap = read_bootstrap();
 148
 149         if (SNOR_BOOT_SUPPORTED) {
 150                 /* Check whether SNOR boot is selected */
 151                 if ((bootstrap & CONFIG_SPEAR_ONLYSNORBOOT) ==
 152                         CONFIG_SPEAR_ONLYSNORBOOT)
 153                         return TRUE;
 154
 155                 if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
 156                         CONFIG_SPEAR_NORNAND8BOOT)
 157                         return TRUE;
 158
 159                 if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
 160                         CONFIG_SPEAR_NORNAND16BOOT)
 161                         return TRUE;
 162         }
 163
 164         return FALSE;
 165 }
 166
 167 int nand_boot_selected(void)
 168 {
 169         u32 bootstrap = read_bootstrap();
 170
 171         if (NAND_BOOT_SUPPORTED) {
 172                 /* Check whether NAND boot is selected */
 173                 if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
 174                         CONFIG_SPEAR_NORNAND8BOOT)
 175                         return TRUE;
 176
 177                 if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
 178                         CONFIG_SPEAR_NORNAND16BOOT)
 179                         return TRUE;
 180         }
 181
 182         return FALSE;
 183 }
 184
 185 int pnor_boot_selected(void)
 186 {
 187         /* Parallel NOR boot is not selected in any SPEAr600 revision */
 188         return FALSE;
 189 }
 190
 191 int usb_boot_selected(void)
 192 {
 193         u32 bootstrap = read_bootstrap();
 194
 195         if (USB_BOOT_SUPPORTED) {
 196                 /* Check whether USB boot is selected */
 197                 if (!(bootstrap & CONFIG_SPEAR_USBBOOT))
 198                         return TRUE;
 199         }
 200
 201         return FALSE;
 202 }
 203
 204 int tftp_boot_selected(void)
 205 {
 206         /* TFTP boot is not selected in any SPEAr600 revision */
 207         return FALSE;
 208 }
 209
 210 int uart_boot_selected(void)
 211 {
 212         /* UART boot is not selected in any SPEAr600 revision */
 213         return FALSE;
 214 }
 215
 216 int spi_boot_selected(void)
 217 {
 218         /* SPI boot is not selected in any SPEAr600 revision */
 219         return FALSE;
 220 }
 221
 222 int i2c_boot_selected(void)
 223 {
 224         /* I2C boot is not selected in any SPEAr600 revision */
 225         return FALSE;
 226 }
 227
 228 int mmc_boot_selected(void)
 229 {
 230         return FALSE;
 231 }
 232
 233 void plat_late_init(void)
 234 {
 235         spear_late_init();
 236 }