arch/arm/cpu/armv7/am33xx/clock_am33xx.c

   1 /*
   2  * clock_am33xx.c
   3  *
   4  * clocks for AM33XX based boards
   5  *
   6  * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <common.h>
  12 #include <asm/arch/cpu.h>
  13 #include <asm/arch/clock.h>
  14 #include <asm/arch/hardware.h>
  15 #include <asm/io.h>
  16
  17 #define PRCM_MOD_EN             0x2
  18 #define PRCM_FORCE_WAKEUP       0x2
  19 #define PRCM_FUNCTL             0x0
  20
  21 #define PRCM_EMIF_CLK_ACTIVITY  BIT(2)
  22 #define PRCM_L3_GCLK_ACTIVITY   BIT(4)
  23
  24 #define PLL_BYPASS_MODE         0x4
  25 #define ST_MN_BYPASS            0x00000100
  26 #define ST_DPLL_CLK             0x00000001
  27 #define CLK_SEL_MASK            0x7ffff
  28 #define CLK_DIV_MASK            0x1f
  29 #define CLK_DIV2_MASK           0x7f
  30 #define CLK_SEL_SHIFT           0x8
  31 #define CLK_MODE_MASK           0x7
  32 #define CLK_MODE_SEL            0x7
  33 #define DPLL_CLKDCOLDO_GATE_CTRL 0x300
  34
  35 #define OSC     (V_OSCK/1000000)
  36
  37 #define MPUPLL_M        CONFIG_SYS_MPUCLK
  38 #define MPUPLL_N        (OSC - 1)
  39 #define MPUPLL_M2       1
  40
  41 /* Core PLL Fdll = 1 GHZ, */
  42 #define COREPLL_M       1000
  43 #define COREPLL_N       (OSC - 1)
  44
  45 #define COREPLL_M4      10      /* CORE_CLKOUTM4 = 200 MHZ */
  46 #define COREPLL_M5      8       /* CORE_CLKOUTM5 = 250 MHZ */
  47 #define COREPLL_M6      4       /* CORE_CLKOUTM6 = 500 MHZ */
  48
  49 /*
  50  * USB PHY clock is 960 MHZ. Since, this comes directly from Fdll, Fdll
  51  * frequency needs to be set to 960 MHZ. Hence,
  52  * For clkout = 192 MHZ, Fdll = 960 MHZ, divider values are given below
  53  */
  54 #define PERPLL_M        960
  55 #define PERPLL_N        (OSC - 1)
  56 #define PERPLL_M2       5
  57
  58 /* DDR Freq is 266 MHZ for now */
  59 /* Set Fdll = 400 MHZ , Fdll = M * 2 * CLKINP/ N + 1; clkout = Fdll /(2 * M2) */
  60 #define DDRPLL_M        266
  61 #define DDRPLL_N        (OSC - 1)
  62 #define DDRPLL_M2       1
  63
  64 struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
  65 struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;
  66 struct cm_dpll *const cmdpll = (struct cm_dpll *)CM_DPLL;
  67 struct cm_rtc *const cmrtc = (struct cm_rtc *)CM_RTC;
  68
  69 const struct dpll_regs dpll_mpu_regs = {
  70         .cm_clkmode_dpll        = CM_WKUP + 0x88,
  71         .cm_idlest_dpll         = CM_WKUP + 0x20,
  72         .cm_clksel_dpll         = CM_WKUP + 0x2C,
  73         .cm_div_m2_dpll         = CM_WKUP + 0xA8,
  74 };
  75
  76 const struct dpll_regs dpll_core_regs = {
  77         .cm_clkmode_dpll        = CM_WKUP + 0x90,
  78         .cm_idlest_dpll         = CM_WKUP + 0x5C,
  79         .cm_clksel_dpll         = CM_WKUP + 0x68,
  80         .cm_div_m4_dpll         = CM_WKUP + 0x80,
  81         .cm_div_m5_dpll         = CM_WKUP + 0x84,
  82         .cm_div_m6_dpll         = CM_WKUP + 0xD8,
  83 };
  84
  85 const struct dpll_regs dpll_per_regs = {
  86         .cm_clkmode_dpll        = CM_WKUP + 0x8C,
  87         .cm_idlest_dpll         = CM_WKUP + 0x70,
  88         .cm_clksel_dpll         = CM_WKUP + 0x9C,
  89         .cm_div_m2_dpll         = CM_WKUP + 0xAC,
  90 };
  91
  92 const struct dpll_regs dpll_ddr_regs = {
  93         .cm_clkmode_dpll        = CM_WKUP + 0x94,
  94         .cm_idlest_dpll         = CM_WKUP + 0x34,
  95         .cm_clksel_dpll         = CM_WKUP + 0x40,
  96         .cm_div_m2_dpll         = CM_WKUP + 0xA0,
  97 };
  98
  99 struct dpll_params dpll_mpu_opp100 = {
 100                 CONFIG_SYS_MPUCLK, OSC-1, 1, -1, -1, -1, -1};
 101 const struct dpll_params dpll_core_opp100 = {
 102                 1000, OSC-1, -1, -1, 10, 8, 4};
 103 const struct dpll_params dpll_mpu = {
 104                 MPUPLL_M_300, OSC-1, 1, -1, -1, -1, -1};
 105 const struct dpll_params dpll_core = {
 106                 50, OSC-1, -1, -1, 1, 1, 1};
 107 const struct dpll_params dpll_per = {
 108                 960, OSC-1, 5, -1, -1, -1, -1};
 109
 110 const struct dpll_params *get_dpll_mpu_params(void)
 111 {
 112         return &dpll_mpu;
 113 }
 114
 115 const struct dpll_params *get_dpll_core_params(void)
 116 {
 117         return &dpll_core;
 118 }
 119
 120 const struct dpll_params *get_dpll_per_params(void)
 121 {
 122         return &dpll_per;
 123 }
 124
 125 void setup_clocks_for_console(void)
 126 {
 127         clrsetbits_le32(&cmwkup->wkclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
 128                         CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
 129                         CD_CLKCTRL_CLKTRCTRL_SHIFT);
 130
 131         clrsetbits_le32(&cmper->l4hsclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
 132                         CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
 133                         CD_CLKCTRL_CLKTRCTRL_SHIFT);
 134
 135         clrsetbits_le32(&cmwkup->wkup_uart0ctrl,
 136                         MODULE_CLKCTRL_MODULEMODE_MASK,
 137                         MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
 138                         MODULE_CLKCTRL_MODULEMODE_SHIFT);
 139         clrsetbits_le32(&cmper->uart1clkctrl,
 140                         MODULE_CLKCTRL_MODULEMODE_MASK,
 141                         MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
 142                         MODULE_CLKCTRL_MODULEMODE_SHIFT);
 143         clrsetbits_le32(&cmper->uart2clkctrl,
 144                         MODULE_CLKCTRL_MODULEMODE_MASK,
 145                         MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
 146                         MODULE_CLKCTRL_MODULEMODE_SHIFT);
 147         clrsetbits_le32(&cmper->uart3clkctrl,
 148                         MODULE_CLKCTRL_MODULEMODE_MASK,
 149                         MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
 150                         MODULE_CLKCTRL_MODULEMODE_SHIFT);
 151         clrsetbits_le32(&cmper->uart4clkctrl,
 152                         MODULE_CLKCTRL_MODULEMODE_MASK,
 153                         MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
 154                         MODULE_CLKCTRL_MODULEMODE_SHIFT);
 155         clrsetbits_le32(&cmper->uart5clkctrl,
 156                         MODULE_CLKCTRL_MODULEMODE_MASK,
 157                         MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
 158                         MODULE_CLKCTRL_MODULEMODE_SHIFT);
 159 }
 160
 161 void enable_basic_clocks(void)
 162 {
 163         u32 *const clk_domains[] = {
 164                 &cmper->l3clkstctrl,
 165                 &cmper->l4fwclkstctrl,
 166                 &cmper->l3sclkstctrl,
 167                 &cmper->l4lsclkstctrl,
 168                 &cmwkup->wkclkstctrl,
 169                 &cmper->emiffwclkctrl,
 170                 &cmrtc->clkstctrl,
 171                 0
 172         };
 173
 174         u32 *const clk_modules_explicit_en[] = {
 175                 &cmper->l3clkctrl,
 176                 &cmper->l4lsclkctrl,
 177                 &cmper->l4fwclkctrl,
 178                 &cmwkup->wkl4wkclkctrl,
 179                 &cmper->l3instrclkctrl,
 180                 &cmper->l4hsclkctrl,
 181                 &cmwkup->wkgpio0clkctrl,
 182                 &cmwkup->wkctrlclkctrl,
 183                 &cmper->timer2clkctrl,
 184                 &cmper->gpmcclkctrl,
 185                 &cmper->elmclkctrl,
 186                 &cmper->mmc0clkctrl,
 187                 &cmper->mmc1clkctrl,
 188                 &cmwkup->wkup_i2c0ctrl,
 189                 &cmper->gpio1clkctrl,
 190                 &cmper->gpio2clkctrl,
 191                 &cmper->gpio3clkctrl,
 192                 &cmper->i2c1clkctrl,
 193                 &cmper->cpgmac0clkctrl,
 194                 &cmper->spi0clkctrl,
 195                 &cmrtc->rtcclkctrl,
 196                 &cmper->usb0clkctrl,
 197                 &cmper->emiffwclkctrl,
 198                 &cmper->emifclkctrl,
 199                 0
 200         };
 201
 202         do_enable_clocks(clk_domains, clk_modules_explicit_en, 1);
 203
 204         /* Select the Master osc 24 MHZ as Timer2 clock source */
 205         writel(0x1, &cmdpll->clktimer2clk);
 206 }
 207 void mpu_pll_config_val(int mpull_m)
 208 {
 209         u32 clkmode, clksel, div_m2;
 210
 211         clkmode = readl(&cmwkup->clkmoddpllmpu);
 212         clksel = readl(&cmwkup->clkseldpllmpu);
 213         div_m2 = readl(&cmwkup->divm2dpllmpu);
 214
 215         /* Set the PLL to bypass Mode */
 216         writel(PLL_BYPASS_MODE, &cmwkup->clkmoddpllmpu);
 217         while (readl(&cmwkup->idlestdpllmpu) != ST_MN_BYPASS)
 218                 ;
 219
 220         clksel &= ~CLK_SEL_MASK;
 221         clksel |= (mpull_m << CLK_SEL_SHIFT) | MPUPLL_N;
 222         writel(clksel, &cmwkup->clkseldpllmpu);
 223
 224         div_m2 &= ~CLK_DIV_MASK;
 225         div_m2 |= MPUPLL_M2;
 226         writel(div_m2, &cmwkup->divm2dpllmpu);
 227
 228         clkmode &= ~CLK_MODE_MASK;
 229         clkmode |= CLK_MODE_SEL;
 230         writel(clkmode, &cmwkup->clkmoddpllmpu);
 231
 232         while (readl(&cmwkup->idlestdpllmpu) != ST_DPLL_CLK)
 233                 ;
 234 }
 235
 236 void mpu_pll_config(void)
 237 {
 238         mpu_pll_config_val(CONFIG_SYS_MPUCLK);
 239 }
 240
 241 static void core_pll_config_val(int m)
 242 {
 243         u32 clkmode, clksel, div_m4, div_m5, div_m6;
 244
 245         clkmode = readl(&cmwkup->clkmoddpllcore);
 246         clksel = readl(&cmwkup->clkseldpllcore);
 247         div_m4 = readl(&cmwkup->divm4dpllcore);
 248         div_m5 = readl(&cmwkup->divm5dpllcore);
 249         div_m6 = readl(&cmwkup->divm6dpllcore);
 250
 251         /* Set the PLL to bypass Mode */
 252         writel(PLL_BYPASS_MODE, &cmwkup->clkmoddpllcore);
 253
 254         while (readl(&cmwkup->idlestdpllcore) != ST_MN_BYPASS)
 255                 ;
 256
 257         clksel &= ~CLK_SEL_MASK;
 258         clksel |= ((m << CLK_SEL_SHIFT) | COREPLL_N);
 259         writel(clksel, &cmwkup->clkseldpllcore);
 260
 261         div_m4 &= ~CLK_DIV_MASK;
 262         div_m4 |= COREPLL_M4;
 263         writel(div_m4, &cmwkup->divm4dpllcore);
 264
 265         div_m5 &= ~CLK_DIV_MASK;
 266         div_m5 |= COREPLL_M5;
 267         writel(div_m5, &cmwkup->divm5dpllcore);
 268
 269         div_m6 &= ~CLK_DIV_MASK;
 270         div_m6 |= COREPLL_M6;
 271         writel(div_m6, &cmwkup->divm6dpllcore);
 272
 273         clkmode &= ~CLK_MODE_MASK;
 274         clkmode |= CLK_MODE_SEL;
 275         writel(clkmode, &cmwkup->clkmoddpllcore);
 276
 277         while (readl(&cmwkup->idlestdpllcore) != ST_DPLL_CLK)
 278                 ;
 279 }
 280
 281 static inline void core_pll_config(void)
 282 {
 283         core_pll_config_val(COREPLL_M);
 284 }
 285
 286 static void per_pll_config_val(int m)
 287 {
 288         u32 clkmode, clksel, div_m2;
 289
 290         clkmode = readl(&cmwkup->clkmoddpllper);
 291         clksel = readl(&cmwkup->clkseldpllper);
 292         div_m2 = readl(&cmwkup->divm2dpllper);
 293
 294         /* Set the PLL to bypass Mode */
 295         writel(PLL_BYPASS_MODE, &cmwkup->clkmoddpllper);
 296
 297         while (readl(&cmwkup->idlestdpllper) != ST_MN_BYPASS)
 298                 ;
 299
 300         clksel &= ~CLK_SEL_MASK;
 301         clksel |= (m << CLK_SEL_SHIFT) | PERPLL_N;
 302         writel(clksel, &cmwkup->clkseldpllper);
 303
 304         div_m2 &= ~CLK_DIV2_MASK;
 305         div_m2 |= PERPLL_M2;
 306         writel(div_m2, &cmwkup->divm2dpllper);
 307
 308         clkmode &= ~CLK_MODE_MASK;
 309         clkmode |= CLK_MODE_SEL;
 310         writel(clkmode, &cmwkup->clkmoddpllper);
 311
 312         while (readl(&cmwkup->idlestdpllper) != ST_DPLL_CLK)
 313                 ;
 314
 315         writel(DPLL_CLKDCOLDO_GATE_CTRL, &cmwkup->clkdcoldodpllper);
 316 }
 317
 318 static inline void per_pll_config(void)
 319 {
 320         per_pll_config_val(PERPLL_M);
 321 }
 322
 323 static void disp_pll_config_val(int m)
 324 {
 325         u32 clkmode, clksel, div_m2;
 326
 327         clkmode = readl(&cmwkup->clkmoddplldisp);
 328         clksel = readl(&cmwkup->clkseldplldisp);
 329         div_m2 = readl(&cmwkup->divm2dplldisp);
 330
 331         /* Set the PLL to bypass Mode */
 332         writel(PLL_BYPASS_MODE, &cmwkup->clkmoddplldisp);
 333
 334         while (!(readl(&cmwkup->idlestdplldisp) & ST_MN_BYPASS))
 335                 ;
 336
 337         clksel &= ~CLK_SEL_MASK;
 338         clksel |= (m << CLK_SEL_SHIFT) | DISPPLL_N;
 339         writel(clksel, &cmwkup->clkseldplldisp);
 340
 341         div_m2 &= ~CLK_DIV2_MASK;
 342         div_m2 |= DISPPLL_M2;
 343         writel(div_m2, &cmwkup->divm2dplldisp);
 344
 345         clkmode &= ~CLK_MODE_MASK;
 346         clkmode |= CLK_MODE_SEL;
 347         writel(clkmode, &cmwkup->clkmoddplldisp);
 348
 349         while (!(readl(&cmwkup->idlestdplldisp) & ST_DPLL_CLK))
 350                 ;
 351 }
 352
 353 static inline void disp_pll_config(void)
 354 {
 355         disp_pll_config_val(DISPPLL_M);
 356 }
 357
 358 void ddr_pll_config(unsigned int ddrpll_m)
 359 {
 360         u32 clkmode, clksel, div_m2;
 361
 362         clkmode = readl(&cmwkup->clkmoddpllddr);
 363         clksel = readl(&cmwkup->clkseldpllddr);
 364         div_m2 = readl(&cmwkup->divm2dpllddr);
 365
 366         /* Set the PLL to bypass Mode */
 367         clkmode &= ~CLK_MODE_MASK;
 368         clkmode |= PLL_BYPASS_MODE;
 369         writel(clkmode, &cmwkup->clkmoddpllddr);
 370
 371         /* Wait till bypass mode is enabled */
 372         while (!(readl(&cmwkup->idlestdpllddr) & ST_MN_BYPASS))
 373                 ;
 374
 375         clksel &= ~CLK_SEL_MASK;
 376         clksel |= (ddrpll_m << CLK_SEL_SHIFT) | DDRPLL_N;
 377         writel(clksel, &cmwkup->clkseldpllddr);
 378
 379         div_m2 &= ~CLK_DIV_MASK;
 380         div_m2 |= DDRPLL_M2;
 381         writel(div_m2, &cmwkup->divm2dpllddr);
 382
 383         clkmode &= ~CLK_MODE_MASK;
 384         clkmode |= CLK_MODE_SEL;
 385         writel(clkmode, &cmwkup->clkmoddpllddr);
 386
 387         /* Wait till dpll is locked */
 388         while ((readl(&cmwkup->idlestdpllddr) & ST_DPLL_CLK) != ST_DPLL_CLK)
 389                 ;
 390 }
 391
 392 #define M(mn) (((mn) & CLK_SEL_MASK) >> CLK_SEL_SHIFT)
 393 #define N(mn) ((mn) & CLK_DIV2_MASK)
 394
 395 unsigned long __clk_get_rate(u32 m_n, u32 div_m2)
 396 {
 397         unsigned long rate;
 398
 399         div_m2 &= CLK_DIV_MASK;
 400         debug("M=%u N=%u M2=%u\n", M(m_n), N(m_n), div_m2);
 401         rate = V_OSCK / 1000 * M(m_n) / (N(m_n) + 1) / div_m2;
 402         debug("CLK = %lu.%03luMHz\n", rate / 1000, rate % 1000);
 403         return rate * 1000;
 404 }
 405
 406 unsigned long lcdc_clk_rate(void)
 407 {
 408         return clk_get_rate(cmwkup, disp);
 409 }
 410
 411 unsigned long mpu_clk_rate(void)
 412 {
 413         return clk_get_rate(cmwkup, mpu);
 414 }
 415
 416 enum {
 417         CLK_MPU_PLL,
 418         CLK_CORE_PLL,
 419         CLK_PER_PLL,
 420         CLK_DISP_PLL,
 421         CLK_GPMC,
 422 };
 423
 424 static struct clk_lookup {
 425         const char *name;
 426         unsigned int index;
 427 } am33xx_clk_lookup[] = {
 428         { "mpu", CLK_MPU_PLL, },
 429         { "core", CLK_CORE_PLL, },
 430         { "per", CLK_PER_PLL, },
 431         { "lcdc", CLK_DISP_PLL, },
 432         { "gpmc", CLK_GPMC, },
 433 };
 434
 435 #define print_pll(dom, pll) {                           \
 436         u32 __pll = clk_get_rate(dom, pll);             \
 437         printf("%-12s %4d.%03d MHz\n", #pll,            \
 438                 __pll / 1000000, __pll / 1000 % 1000);  \
 439         }
 440
 441 #define print_pll2(dom, n, pll) {                       \
 442         u32 __m_n = readl(&(dom)->clkseldpll##pll);     \
 443         u32 __div = readl(&(dom)->divm##n##dpll##pll);  \
 444         u32 __pll = __clk_get_rate(__m_n, __div);       \
 445         printf("%-12s %4d.%03d MHz\n", #pll "_m" #n,    \
 446                 __pll / 1000000, __pll / 1000 % 1000);  \
 447         }
 448
 449 static void do_showclocks(void)
 450 {
 451         print_pll(cmwkup, mpu);
 452         print_pll2(cmwkup, 4, core);
 453         print_pll2(cmwkup, 5, core);
 454         print_pll2(cmwkup, 6, core);
 455         print_pll(cmwkup, ddr);
 456         print_pll(cmwkup, per);
 457         print_pll(cmwkup, disp);
 458 }
 459
 460 int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc,
 461         char *const argv[])
 462 {
 463         int i;
 464         unsigned long freq;
 465         unsigned long __attribute__((unused)) ref = ~0UL;
 466
 467         if (argc < 2) {
 468                 do_showclocks();
 469                 return CMD_RET_SUCCESS;
 470         } else if (argc == 2 || argc > 4) {
 471                 return CMD_RET_USAGE;
 472         }
 473
 474         freq = simple_strtoul(argv[2], NULL, 0);
 475         if (freq < 1000) {
 476                 printf("Invalid clock frequency %lu\n", freq);
 477                 return CMD_RET_FAILURE;
 478         }
 479         if (argc > 3) {
 480                 ref = simple_strtoul(argv[3], NULL, 0);
 481         }
 482         for (i = 0; i < ARRAY_SIZE(am33xx_clk_lookup); i++) {
 483                 if (strcasecmp(argv[1], am33xx_clk_lookup[i].name) == 0) {
 484                         switch (am33xx_clk_lookup[i].index) {
 485                         case CLK_MPU_PLL:
 486                                 mpu_pll_config_val(freq / 1000000);
 487                                 break;
 488                         case CLK_CORE_PLL:
 489                                 core_pll_config_val(freq / 1000000);
 490                                 break;
 491                         case CLK_PER_PLL:
 492                                 per_pll_config_val(freq / 1000000);
 493                                 break;
 494                         case CLK_DISP_PLL:
 495                                 disp_pll_config_val(freq / 1000000);
 496                                 break;
 497                         default:
 498                                 printf("Cannot change %s clock\n",
 499                                         am33xx_clk_lookup[i].name);
 500                                 return CMD_RET_FAILURE;
 501                         }
 502
 503                         printf("%s clock set to %lu.%03lu MHz\n",
 504                                 am33xx_clk_lookup[i].name,
 505                                 freq / 1000000, freq / 1000 % 1000);
 506                         return CMD_RET_SUCCESS;
 507                 }
 508         }
 509         if (i == ARRAY_SIZE(am33xx_clk_lookup)) {
 510                 printf("clock %s not found; supported clocks are:\n", argv[1]);
 511                 for (i = 0; i < ARRAY_SIZE(am33xx_clk_lookup); i++) {
 512                         printf("\t%s\n", am33xx_clk_lookup[i].name);
 513                 }
 514         } else {
 515                 printf("Failed to set clock %s to %s MHz\n",
 516                         argv[1], argv[2]);
 517         }
 518         return CMD_RET_FAILURE;
 519 }
 520
 521 U_BOOT_CMD(
 522         clocks, 4, 0, do_clocks,
 523         "display/set clocks",
 524         "                    - display clock settings\n"
 525         "clocks <clkname> <freq>    - set clock <clkname> to <freq> Hz"
 526 );