arch/arm/cpu/armv7/am33xx/clock_am43xx.c

   1 /*
   2  * clock_am43xx.c
   3  *
   4  * clocks for AM43XX based boards
   5  * Derived from AM33XX based boards
   6  *
   7  * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
   8  *
   9  * SPDX-License-Identifier:     GPL-2.0+
  10  */
  11
  12 #include <common.h>
  13 #include <asm/arch/cpu.h>
  14 #include <asm/arch/clock.h>
  15 #include <asm/arch/hardware.h>
  16 #include <asm/arch/sys_proto.h>
  17 #include <asm/io.h>
  18
  19 struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
  20 struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;
  21 struct cm_dpll *const cmdpll = (struct cm_dpll *)CM_DPLL;
  22
  23 const struct dpll_regs dpll_mpu_regs = {
  24         .cm_clkmode_dpll        = CM_WKUP + 0x560,
  25         .cm_idlest_dpll         = CM_WKUP + 0x564,
  26         .cm_clksel_dpll         = CM_WKUP + 0x56c,
  27         .cm_div_m2_dpll         = CM_WKUP + 0x570,
  28 };
  29
  30 const struct dpll_regs dpll_core_regs = {
  31         .cm_clkmode_dpll        = CM_WKUP + 0x520,
  32         .cm_idlest_dpll         = CM_WKUP + 0x524,
  33         .cm_clksel_dpll         = CM_WKUP + 0x52C,
  34         .cm_div_m4_dpll         = CM_WKUP + 0x538,
  35         .cm_div_m5_dpll         = CM_WKUP + 0x53C,
  36         .cm_div_m6_dpll         = CM_WKUP + 0x540,
  37 };
  38
  39 const struct dpll_regs dpll_per_regs = {
  40         .cm_clkmode_dpll        = CM_WKUP + 0x5E0,
  41         .cm_idlest_dpll         = CM_WKUP + 0x5E4,
  42         .cm_clksel_dpll         = CM_WKUP + 0x5EC,
  43         .cm_div_m2_dpll         = CM_WKUP + 0x5F0,
  44 };
  45
  46 const struct dpll_regs dpll_ddr_regs = {
  47         .cm_clkmode_dpll        = CM_WKUP + 0x5A0,
  48         .cm_idlest_dpll         = CM_WKUP + 0x5A4,
  49         .cm_clksel_dpll         = CM_WKUP + 0x5AC,
  50         .cm_div_m2_dpll         = CM_WKUP + 0x5B0,
  51         .cm_div_m4_dpll         = CM_WKUP + 0x5B8,
  52 };
  53
  54 void setup_clocks_for_console(void)
  55 {
  56         /* Do not add any spl_debug prints in this function */
  57         clrsetbits_le32(&cmwkup->wkclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
  58                         CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
  59                         CD_CLKCTRL_CLKTRCTRL_SHIFT);
  60
  61         /* Enable UART0 */
  62         clrsetbits_le32(&cmwkup->wkup_uart0ctrl,
  63                         MODULE_CLKCTRL_MODULEMODE_MASK,
  64                         MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
  65                         MODULE_CLKCTRL_MODULEMODE_SHIFT);
  66 }
  67
  68 void enable_basic_clocks(void)
  69 {
  70         u32 *const clk_domains[] = {
  71                 &cmper->l3clkstctrl,
  72                 &cmper->l3sclkstctrl,
  73                 &cmper->l4lsclkstctrl,
  74                 &cmwkup->wkclkstctrl,
  75                 &cmper->emifclkstctrl,
  76                 0
  77         };
  78
  79         u32 *const clk_modules_explicit_en[] = {
  80                 &cmper->l3clkctrl,
  81                 &cmper->l4lsclkctrl,
  82                 &cmper->l4fwclkctrl,
  83                 &cmwkup->wkl4wkclkctrl,
  84                 &cmper->l3instrclkctrl,
  85                 &cmper->l4hsclkctrl,
  86                 &cmwkup->wkgpio0clkctrl,
  87                 &cmwkup->wkctrlclkctrl,
  88                 &cmper->timer2clkctrl,
  89                 &cmper->gpmcclkctrl,
  90                 &cmper->elmclkctrl,
  91                 &cmper->mmc0clkctrl,
  92                 &cmper->mmc1clkctrl,
  93                 &cmwkup->wkup_i2c0ctrl,
  94                 &cmper->gpio1clkctrl,
  95                 &cmper->gpio2clkctrl,
  96                 &cmper->gpio3clkctrl,
  97                 &cmper->gpio4clkctrl,
  98                 &cmper->gpio5clkctrl,
  99                 &cmper->i2c1clkctrl,
 100                 &cmper->emiffwclkctrl,
 101                 &cmper->emifclkctrl,
 102                 &cmper->otfaemifclkctrl,
 103                 0
 104         };
 105
 106         do_enable_clocks(clk_domains, clk_modules_explicit_en, 1);
 107
 108         /* Select the Master osc clk as Timer2 clock source */
 109         writel(0x1, &cmdpll->clktimer2clk);
 110 }