arch/arm/cpu/armv7/am33xx/emif4.c

   1 /*
   2  * emif4.c
   3  *
   4  * AM33XX emif4 configuration file
   5  *
   6  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <common.h>
  12 #include <asm/arch/cpu.h>
  13 #include <asm/arch/ddr_defs.h>
  14 #include <asm/arch/hardware.h>
  15 #include <asm/arch/clock.h>
  16 #include <asm/arch/sys_proto.h>
  17 #include <asm/io.h>
  18 #include <asm/emif.h>
  19
  20 DECLARE_GLOBAL_DATA_PTR;
  21
  22 int dram_init(void)
  23 {
  24         /* dram_init must store complete ramsize in gd->ram_size */
  25         gd->ram_size = get_ram_size(
  26                         (void *)CONFIG_SYS_SDRAM_BASE,
  27                         CONFIG_MAX_RAM_BANK_SIZE);
  28         return 0;
  29 }
  30
  31 void dram_init_banksize(void)
  32 {
  33         gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
  34         gd->bd->bi_dram[0].size = gd->ram_size;
  35 }
  36
  37
  38 #if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
  39 #ifdef CONFIG_TI81XX
  40 static struct dmm_lisa_map_regs *hw_lisa_map_regs =
  41                                 (struct dmm_lisa_map_regs *)DMM_BASE;
  42 #endif
  43 #ifndef CONFIG_TI816X
  44 static struct vtp_reg *vtpreg[2] = {
  45                                 (struct vtp_reg *)VTP0_CTRL_ADDR,
  46                                 (struct vtp_reg *)VTP1_CTRL_ADDR};
  47 #endif
  48 #ifdef CONFIG_AM33XX
  49 static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
  50 #endif
  51
  52 #ifdef CONFIG_TI81XX
  53 void config_dmm(const struct dmm_lisa_map_regs *regs)
  54 {
  55         enable_dmm_clocks();
  56
  57         writel(0, &hw_lisa_map_regs->dmm_lisa_map_3);
  58         writel(0, &hw_lisa_map_regs->dmm_lisa_map_2);
  59         writel(0, &hw_lisa_map_regs->dmm_lisa_map_1);
  60         writel(0, &hw_lisa_map_regs->dmm_lisa_map_0);
  61
  62         writel(regs->dmm_lisa_map_3, &hw_lisa_map_regs->dmm_lisa_map_3);
  63         writel(regs->dmm_lisa_map_2, &hw_lisa_map_regs->dmm_lisa_map_2);
  64         writel(regs->dmm_lisa_map_1, &hw_lisa_map_regs->dmm_lisa_map_1);
  65         writel(regs->dmm_lisa_map_0, &hw_lisa_map_regs->dmm_lisa_map_0);
  66 }
  67 #endif
  68
  69 #ifndef CONFIG_TI816X
  70 static void config_vtp(int nr)
  71 {
  72         writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_ENABLE,
  73                         &vtpreg[nr]->vtp0ctrlreg);
  74         writel(readl(&vtpreg[nr]->vtp0ctrlreg) & (~VTP_CTRL_START_EN),
  75                         &vtpreg[nr]->vtp0ctrlreg);
  76         writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_START_EN,
  77                         &vtpreg[nr]->vtp0ctrlreg);
  78
  79         /* Poll for READY */
  80         while ((readl(&vtpreg[nr]->vtp0ctrlreg) & VTP_CTRL_READY) !=
  81                         VTP_CTRL_READY)
  82                 ;
  83 }
  84 #endif
  85
  86 void __weak ddr_pll_config(unsigned int ddrpll_m)
  87 {
  88 }
  89
  90 void config_ddr(unsigned int pll, unsigned int ioctrl,
  91                 const struct ddr_data *data, const struct cmd_control *ctrl,
  92                 const struct emif_regs *regs, int nr)
  93 {
  94         ddr_pll_config(pll);
  95 #ifndef CONFIG_TI816X
  96         config_vtp(nr);
  97 #endif
  98         config_cmd_ctrl(ctrl, nr);
  99
 100         config_ddr_data(data, nr);
 101 #ifdef CONFIG_AM33XX
 102         config_io_ctrl(ioctrl);
 103
 104         /* Set CKE to be controlled by EMIF/DDR PHY */
 105         writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
 106 #endif
 107
 108         /* Program EMIF instance */
 109         config_ddr_phy(regs, nr);
 110         set_sdram_timings(regs, nr);
 111         config_sdram(regs, nr);
 112 }
 113 #endif