3 * Texas Instruments, <www.ti.com>
4 * Aneesh V <aneesh@ti.com>
6 * SPDX-License-Identifier: GPL-2.0+
8 #include <linux/types.h>
10 #include <asm/armv7.h>
11 #include <asm/utils.h>
13 #define ARMV7_DCACHE_INVAL_ALL 1
14 #define ARMV7_DCACHE_CLEAN_INVAL_ALL 2
15 #define ARMV7_DCACHE_INVAL_RANGE 3
16 #define ARMV7_DCACHE_CLEAN_INVAL_RANGE 4
18 #ifndef CONFIG_SYS_DCACHE_OFF
20 * Write the level and type you want to Cache Size Selection Register(CSSELR)
21 * to get size details from Current Cache Size ID Register(CCSIDR)
23 static void set_csselr(u32 level, u32 type)
24 { u32 csselr = level << 1 | type;
26 /* Write to Cache Size Selection Register(CSSELR) */
27 asm volatile ("mcr p15, 2, %0, c0, c0, 0" : : "r" (csselr));
30 static u32 get_ccsidr(void)
34 /* Read current CP15 Cache Size ID Register */
35 asm volatile ("mrc p15, 1, %0, c0, c0, 0" : "=r" (ccsidr));
39 static u32 get_clidr(void)
43 /* Read current CP15 Cache Level ID Register */
44 asm volatile ("mrc p15,1,%0,c0,c0,1" : "=r" (clidr));
48 static void v7_inval_dcache_level_setway(u32 level, u32 num_sets,
49 u32 num_ways, u32 way_shift,
55 * For optimal assembly code:
57 * b. have bigger loop inside
59 for (way = num_ways - 1; way >= 0 ; way--) {
60 for (set = num_sets - 1; set >= 0; set--) {
61 setway = (level << 1) | (set << log2_line_len) |
63 /* Invalidate data/unified cache line by set/way */
64 asm volatile (" mcr p15, 0, %0, c7, c6, 2"
68 /* DSB to make sure the operation is complete */
72 static void v7_clean_inval_dcache_level_setway(u32 level, u32 num_sets,
73 u32 num_ways, u32 way_shift,
79 * For optimal assembly code:
81 * b. have bigger loop inside
83 for (way = num_ways - 1; way >= 0 ; way--) {
84 for (set = num_sets - 1; set >= 0; set--) {
85 setway = (level << 1) | (set << log2_line_len) |
88 * Clean & Invalidate data/unified
89 * cache line by set/way
91 asm volatile (" mcr p15, 0, %0, c7, c14, 2"
95 /* DSB to make sure the operation is complete */
99 static void v7_maint_dcache_level_setway(u32 level, u32 operation)
102 u32 num_sets, num_ways, log2_line_len, log2_num_ways;
105 set_csselr(level, ARMV7_CSSELR_IND_DATA_UNIFIED);
107 ccsidr = get_ccsidr();
109 log2_line_len = ((ccsidr & CCSIDR_LINE_SIZE_MASK) >>
110 CCSIDR_LINE_SIZE_OFFSET) + 2;
111 /* Converting from words to bytes */
114 num_ways = ((ccsidr & CCSIDR_ASSOCIATIVITY_MASK) >>
115 CCSIDR_ASSOCIATIVITY_OFFSET) + 1;
116 num_sets = ((ccsidr & CCSIDR_NUM_SETS_MASK) >>
117 CCSIDR_NUM_SETS_OFFSET) + 1;
119 * According to ARMv7 ARM number of sets and number of ways need
120 * not be a power of 2
122 log2_num_ways = log_2_n_round_up(num_ways);
124 way_shift = (32 - log2_num_ways);
125 if (operation == ARMV7_DCACHE_INVAL_ALL) {
126 v7_inval_dcache_level_setway(level, num_sets, num_ways,
127 way_shift, log2_line_len);
128 } else if (operation == ARMV7_DCACHE_CLEAN_INVAL_ALL) {
129 v7_clean_inval_dcache_level_setway(level, num_sets, num_ways,
130 way_shift, log2_line_len);
134 static void v7_maint_dcache_all(u32 operation)
136 u32 level, cache_type, level_start_bit = 0;
138 u32 clidr = get_clidr();
140 for (level = 0; level < 7; level++) {
141 cache_type = (clidr >> level_start_bit) & 0x7;
142 if ((cache_type == ARMV7_CLIDR_CTYPE_DATA_ONLY) ||
143 (cache_type == ARMV7_CLIDR_CTYPE_INSTRUCTION_DATA) ||
144 (cache_type == ARMV7_CLIDR_CTYPE_UNIFIED))
145 v7_maint_dcache_level_setway(level, operation);
146 level_start_bit += 3;
150 static void v7_dcache_clean_inval_range(u32 start,
151 u32 stop, u32 line_len)
155 /* Align start to cache line boundary */
156 start &= ~(line_len - 1);
157 for (mva = start; mva < stop; mva = mva + line_len) {
158 /* DCCIMVAC - Clean & Invalidate data cache by MVA to PoC */
159 asm volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" (mva));
163 static void v7_dcache_inval_range(u32 start, u32 stop, u32 line_len)
168 * If start address is not aligned to cache-line do not
169 * invalidate the first cache-line
171 if (start & (line_len - 1)) {
172 printf("ERROR: %s - start address is not aligned - 0x%08x\n",
174 /* move to next cache line */
175 start = (start + line_len - 1) & ~(line_len - 1);
179 * If stop address is not aligned to cache-line do not
180 * invalidate the last cache-line
182 if (stop & (line_len - 1)) {
183 printf("ERROR: %s - stop address is not aligned - 0x%08x\n",
185 /* align to the beginning of this cache line */
186 stop &= ~(line_len - 1);
189 for (mva = start; mva < stop; mva = mva + line_len) {
190 /* DCIMVAC - Invalidate data cache by MVA to PoC */
191 asm volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" (mva));
195 static void v7_dcache_maint_range(u32 start, u32 stop, u32 range_op)
197 u32 line_len, ccsidr;
199 ccsidr = get_ccsidr();
200 line_len = ((ccsidr & CCSIDR_LINE_SIZE_MASK) >>
201 CCSIDR_LINE_SIZE_OFFSET) + 2;
202 /* Converting from words to bytes */
204 /* converting from log2(linelen) to linelen */
205 line_len = 1 << line_len;
208 case ARMV7_DCACHE_CLEAN_INVAL_RANGE:
209 v7_dcache_clean_inval_range(start, stop, line_len);
211 case ARMV7_DCACHE_INVAL_RANGE:
212 v7_dcache_inval_range(start, stop, line_len);
216 /* DSB to make sure the operation is complete */
221 static void v7_inval_tlb(void)
224 /* Invalidate entire unified TLB */
225 "mcr p15, 0, %0, c8, c7, 0\n"
226 /* Invalidate entire data TLB */
227 "mcr p15, 0, %0, c8, c6, 0\n"
228 /* Invalidate entire instruction TLB */
229 "mcr p15, 0, %0, c8, c5, 0\n"
230 /* Full system DSB - make sure that the invalidation is complete */
231 "mcr p15, 0, %0, c7, c10, 4\n"
232 /* Full system ISB - make sure the instruction stream sees it */
233 "mcr p15, 0, %0, c7, c5, 4\n"
237 void invalidate_dcache_all(void)
239 v7_maint_dcache_all(ARMV7_DCACHE_INVAL_ALL);
241 v7_outer_cache_inval_all();
245 * Performs a clean & invalidation of the entire data cache
248 void flush_dcache_all(void)
250 v7_maint_dcache_all(ARMV7_DCACHE_CLEAN_INVAL_ALL);
252 v7_outer_cache_flush_all();
256 * Invalidates range in all levels of D-cache/unified cache used:
257 * Affects the range [start, stop - 1]
259 void invalidate_dcache_range(unsigned long start, unsigned long stop)
262 v7_dcache_maint_range(start, stop, ARMV7_DCACHE_INVAL_RANGE);
264 v7_outer_cache_inval_range(start, stop);
268 * Flush range(clean & invalidate) from all levels of D-cache/unified
270 * Affects the range [start, stop - 1]
272 void flush_dcache_range(unsigned long start, unsigned long stop)
274 v7_dcache_maint_range(start, stop, ARMV7_DCACHE_CLEAN_INVAL_RANGE);
276 v7_outer_cache_flush_range(start, stop);
279 void arm_init_before_mmu(void)
281 v7_outer_cache_enable();
282 invalidate_dcache_all();
286 void mmu_page_table_flush(unsigned long start, unsigned long stop)
288 flush_dcache_range(start, stop);
293 * Flush range from all levels of d-cache/unified-cache used:
294 * Affects the range [start, start + size - 1]
296 void flush_cache(unsigned long start, unsigned long size)
298 flush_dcache_range(start, start + size);
300 #else /* #ifndef CONFIG_SYS_DCACHE_OFF */
301 void invalidate_dcache_all(void)
305 void flush_dcache_all(void)
309 void invalidate_dcache_range(unsigned long start, unsigned long stop)
313 void flush_dcache_range(unsigned long start, unsigned long stop)
317 void arm_init_before_mmu(void)
321 void flush_cache(unsigned long start, unsigned long size)
325 void mmu_page_table_flush(unsigned long start, unsigned long stop)
329 void arm_init_domains(void)
332 #endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
334 #ifndef CONFIG_SYS_ICACHE_OFF
335 /* Invalidate entire I-cache and branch predictor array */
336 void invalidate_icache_all(void)
339 * Invalidate all instruction caches to PoU.
340 * Also flushes branch target cache.
343 "mcr p15, 0, %0, c7, c5, 0\n"
344 /* Invalidate entire branch predictor array */
345 "mcr p15, 0, %0, c7, c5, 6\n"
346 /* Full system DSB - make sure that the invalidation is complete */
347 "mcr p15, 0, %0, c7, c10, 4\n"
348 /* ISB - make sure the instruction stream sees it */
349 "mcr p15, 0, %0, c7, c5, 4\n"
353 void invalidate_icache_all(void)
359 * Stub implementations for outer cache operations
361 void __v7_outer_cache_enable(void)
364 void v7_outer_cache_enable(void)
365 __attribute__((weak, alias("__v7_outer_cache_enable")));
367 void __v7_outer_cache_disable(void)
370 void v7_outer_cache_disable(void)
371 __attribute__((weak, alias("__v7_outer_cache_disable")));
373 void __v7_outer_cache_flush_all(void)
376 void v7_outer_cache_flush_all(void)
377 __attribute__((weak, alias("__v7_outer_cache_flush_all")));
379 void __v7_outer_cache_inval_all(void)
382 void v7_outer_cache_inval_all(void)
383 __attribute__((weak, alias("__v7_outer_cache_inval_all")));
385 void __v7_outer_cache_flush_range(u32 start, u32 end)
388 void v7_outer_cache_flush_range(u32 start, u32 end)
389 __attribute__((weak, alias("__v7_outer_cache_flush_range")));
391 void __v7_outer_cache_inval_range(u32 start, u32 end)
394 void v7_outer_cache_inval_range(u32 start, u32 end)
395 __attribute__((weak, alias("__v7_outer_cache_inval_range")));