2 * Clock setup for SMDK5250 board based on EXYNOS5
4 * Copyright (C) 2012 Samsung Electronics
6 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/clk.h>
13 #include <asm/arch/clock.h>
14 #include <asm/arch/spl.h>
15 #include <asm/arch/dwmmc.h>
17 #include "clock_init.h"
18 #include "common_setup.h"
19 #include "exynos5_setup.h"
21 #define FSYS1_MMC0_DIV_MASK 0xff0f
22 #define FSYS1_MMC0_DIV_VAL 0x0701
24 DECLARE_GLOBAL_DATA_PTR;
26 struct arm_clk_ratios arm_clk_ratios[] = {
27 #ifdef CONFIG_EXYNOS5420
37 .pclk_dbg_ratio = 0x6,
54 .pclk_dbg_ratio = 0x1,
69 .pclk_dbg_ratio = 0x1,
84 .pclk_dbg_ratio = 0x1,
99 .pclk_dbg_ratio = 0x1,
106 .arm_freq_mhz = 1400,
114 .pclk_dbg_ratio = 0x1,
121 .arm_freq_mhz = 1700,
129 .pclk_dbg_ratio = 0x1,
139 struct mem_timings mem_timings[] = {
140 #ifdef CONFIG_EXYNOS5420
142 .mem_manuf = MEM_MANUF_SAMSUNG,
143 .mem_type = DDR_MODE_DDR3,
144 .frequency_mhz = 800,
188 0x00020018, 0x00030000, 0x00010046, 0x00000d70,
191 .timing_ref = 0x000000bb,
192 .timing_row = 0x6836650f,
193 .timing_data = 0x3630580b,
194 .timing_power = 0x41000a26,
195 .phy0_dqs = 0x08080808,
196 .phy1_dqs = 0x08080808,
197 .phy0_dq = 0x08080808,
198 .phy1_dq = 0x08080808,
201 .phy0_pulld_dqs = 0xf,
202 .phy1_pulld_dqs = 0xf,
204 .lpddr3_ctrl_phy_reset = 0x1,
205 .ctrl_start_point = 0x10,
227 * Dynamic Clock: Always Running
228 * Memory Burst length: 8
230 * Memory Bus width: 32 bit
232 * Additional Latancy for PLL: 0 Cycle
234 .memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE |
235 DMC_MEMCONTROL_DPWRDN_DISABLE |
236 DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE |
237 DMC_MEMCONTROL_TP_DISABLE |
238 DMC_MEMCONTROL_DSREF_DISABLE |
239 DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) |
240 DMC_MEMCONTROL_MEM_TYPE_DDR3 |
241 DMC_MEMCONTROL_MEM_WIDTH_32BIT |
242 DMC_MEMCONTROL_NUM_CHIP_1 |
243 DMC_MEMCONTROL_BL_8 |
244 DMC_MEMCONTROL_PZQ_DISABLE |
245 DMC_MEMCONTROL_MRR_BYTE_7_0,
246 .memconfig = DMC_MEMCONFIG_CHIP_MAP_SPLIT |
247 DMC_MEMCONFIGX_CHIP_COL_10 |
248 DMC_MEMCONFIGX_CHIP_ROW_15 |
249 DMC_MEMCONFIGX_CHIP_BANK_8,
250 .prechconfig_tp_cnt = 0xff,
253 .concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE |
254 DMC_CONCONTROL_TIMEOUT_LEVEL0 |
255 DMC_CONCONTROL_RD_FETCH_DISABLE |
256 DMC_CONCONTROL_EMPTY_DISABLE |
257 DMC_CONCONTROL_AREF_EN_DISABLE |
258 DMC_CONCONTROL_IO_PD_CON_DISABLE,
260 .chips_per_channel = 1,
261 .chips_to_configure = 1,
263 .gate_leveling_enable = 1,
264 .read_leveling_enable = 0,
268 .mem_manuf = MEM_MANUF_ELPIDA,
269 .mem_type = DDR_MODE_DDR3,
270 .frequency_mhz = 800,
290 .pclk_cdrex_ratio = 0x5,
292 0x00020018, 0x00030000, 0x00010042, 0x00000d70
294 .timing_ref = 0x000000bb,
295 .timing_row = 0x8c36650e,
296 .timing_data = 0x3630580b,
297 .timing_power = 0x41000a44,
298 .phy0_dqs = 0x08080808,
299 .phy1_dqs = 0x08080808,
300 .phy0_dq = 0x08080808,
301 .phy1_dq = 0x08080808,
304 .phy0_pulld_dqs = 0xf,
305 .phy1_pulld_dqs = 0xf,
307 .lpddr3_ctrl_phy_reset = 0x1,
308 .ctrl_start_point = 0x10,
330 * Dynamic Clock: Always Running
331 * Memory Burst length: 8
333 * Memory Bus width: 32 bit
335 * Additional Latancy for PLL: 0 Cycle
337 .memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE |
338 DMC_MEMCONTROL_DPWRDN_DISABLE |
339 DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE |
340 DMC_MEMCONTROL_TP_DISABLE |
341 DMC_MEMCONTROL_DSREF_ENABLE |
342 DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) |
343 DMC_MEMCONTROL_MEM_TYPE_DDR3 |
344 DMC_MEMCONTROL_MEM_WIDTH_32BIT |
345 DMC_MEMCONTROL_NUM_CHIP_1 |
346 DMC_MEMCONTROL_BL_8 |
347 DMC_MEMCONTROL_PZQ_DISABLE |
348 DMC_MEMCONTROL_MRR_BYTE_7_0,
349 .memconfig = DMC_MEMCONFIGX_CHIP_MAP_INTERLEAVED |
350 DMC_MEMCONFIGX_CHIP_COL_10 |
351 DMC_MEMCONFIGX_CHIP_ROW_15 |
352 DMC_MEMCONFIGX_CHIP_BANK_8,
353 .membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40),
354 .membaseconfig1 = DMC_MEMBASECONFIG_VAL(0x80),
355 .prechconfig_tp_cnt = 0xff,
358 .concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE |
359 DMC_CONCONTROL_TIMEOUT_LEVEL0 |
360 DMC_CONCONTROL_RD_FETCH_DISABLE |
361 DMC_CONCONTROL_EMPTY_DISABLE |
362 DMC_CONCONTROL_AREF_EN_DISABLE |
363 DMC_CONCONTROL_IO_PD_CON_DISABLE,
365 .chips_per_channel = 2,
366 .chips_to_configure = 1,
368 .impedance = IMP_OUTPUT_DRV_30_OHM,
369 .gate_leveling_enable = 0,
371 .mem_manuf = MEM_MANUF_SAMSUNG,
372 .mem_type = DDR_MODE_DDR3,
373 .frequency_mhz = 800,
393 .pclk_cdrex_ratio = 0x5,
395 0x00020018, 0x00030000, 0x00010000, 0x00000d70
397 .timing_ref = 0x000000bb,
398 .timing_row = 0x8c36650e,
399 .timing_data = 0x3630580b,
400 .timing_power = 0x41000a44,
401 .phy0_dqs = 0x08080808,
402 .phy1_dqs = 0x08080808,
403 .phy0_dq = 0x08080808,
404 .phy1_dq = 0x08080808,
407 .phy0_pulld_dqs = 0xf,
408 .phy1_pulld_dqs = 0xf,
410 .lpddr3_ctrl_phy_reset = 0x1,
411 .ctrl_start_point = 0x10,
433 * Dynamic Clock: Always Running
434 * Memory Burst length: 8
436 * Memory Bus width: 32 bit
438 * Additional Latancy for PLL: 0 Cycle
440 .memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE |
441 DMC_MEMCONTROL_DPWRDN_DISABLE |
442 DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE |
443 DMC_MEMCONTROL_TP_DISABLE |
444 DMC_MEMCONTROL_DSREF_ENABLE |
445 DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) |
446 DMC_MEMCONTROL_MEM_TYPE_DDR3 |
447 DMC_MEMCONTROL_MEM_WIDTH_32BIT |
448 DMC_MEMCONTROL_NUM_CHIP_1 |
449 DMC_MEMCONTROL_BL_8 |
450 DMC_MEMCONTROL_PZQ_DISABLE |
451 DMC_MEMCONTROL_MRR_BYTE_7_0,
452 .memconfig = DMC_MEMCONFIGX_CHIP_MAP_INTERLEAVED |
453 DMC_MEMCONFIGX_CHIP_COL_10 |
454 DMC_MEMCONFIGX_CHIP_ROW_15 |
455 DMC_MEMCONFIGX_CHIP_BANK_8,
456 .membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40),
457 .membaseconfig1 = DMC_MEMBASECONFIG_VAL(0x80),
458 .prechconfig_tp_cnt = 0xff,
461 .concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE |
462 DMC_CONCONTROL_TIMEOUT_LEVEL0 |
463 DMC_CONCONTROL_RD_FETCH_DISABLE |
464 DMC_CONCONTROL_EMPTY_DISABLE |
465 DMC_CONCONTROL_AREF_EN_DISABLE |
466 DMC_CONCONTROL_IO_PD_CON_DISABLE,
468 .chips_per_channel = 2,
469 .chips_to_configure = 1,
471 .impedance = IMP_OUTPUT_DRV_40_OHM,
472 .gate_leveling_enable = 1,
478 * Get the required memory type and speed (SPL version).
480 * In SPL we have no device tree, so we use the machine parameters
482 * @param mem_type Returns memory type
483 * @param frequency_mhz Returns memory speed in MHz
484 * @param arm_freq Returns ARM clock speed in MHz
485 * @param mem_manuf Return Memory Manufacturer name
487 static void clock_get_mem_selection(enum ddr_mode *mem_type,
488 unsigned *frequency_mhz, unsigned *arm_freq,
489 enum mem_manuf *mem_manuf)
491 struct spl_machine_param *params;
493 params = spl_get_machine_params();
494 *mem_type = params->mem_type;
495 *frequency_mhz = params->frequency_mhz;
496 *arm_freq = params->arm_freq_mhz;
497 *mem_manuf = params->mem_manuf;
500 /* Get the ratios for setting ARM clock */
501 struct arm_clk_ratios *get_arm_ratios(void)
503 struct arm_clk_ratios *arm_ratio;
504 enum ddr_mode mem_type;
505 enum mem_manuf mem_manuf;
506 unsigned frequency_mhz, arm_freq;
509 clock_get_mem_selection(&mem_type, &frequency_mhz,
510 &arm_freq, &mem_manuf);
512 for (i = 0, arm_ratio = arm_clk_ratios; i < ARRAY_SIZE(arm_clk_ratios);
514 if (arm_ratio->arm_freq_mhz == arm_freq)
518 /* will hang if failed to find clock ratio */
525 struct mem_timings *clock_get_mem_timings(void)
527 struct mem_timings *mem;
528 enum ddr_mode mem_type;
529 enum mem_manuf mem_manuf;
530 unsigned frequency_mhz, arm_freq;
533 clock_get_mem_selection(&mem_type, &frequency_mhz,
534 &arm_freq, &mem_manuf);
535 for (i = 0, mem = mem_timings; i < ARRAY_SIZE(mem_timings);
537 if (mem->mem_type == mem_type &&
538 mem->frequency_mhz == frequency_mhz &&
539 mem->mem_manuf == mem_manuf)
543 /* will hang if failed to find memory timings */
550 static void exynos5250_system_clock_init(void)
552 struct exynos5_clock *clk =
553 (struct exynos5_clock *)samsung_get_base_clock();
554 struct mem_timings *mem;
555 struct arm_clk_ratios *arm_clk_ratio;
558 mem = clock_get_mem_timings();
559 arm_clk_ratio = get_arm_ratios();
561 clrbits_le32(&clk->src_cpu, MUX_APLL_SEL_MASK);
563 val = readl(&clk->mux_stat_cpu);
564 } while ((val | MUX_APLL_SEL_MASK) != val);
566 clrbits_le32(&clk->src_core1, MUX_MPLL_SEL_MASK);
568 val = readl(&clk->mux_stat_core1);
569 } while ((val | MUX_MPLL_SEL_MASK) != val);
571 clrbits_le32(&clk->src_top2, MUX_CPLL_SEL_MASK);
572 clrbits_le32(&clk->src_top2, MUX_EPLL_SEL_MASK);
573 clrbits_le32(&clk->src_top2, MUX_VPLL_SEL_MASK);
574 clrbits_le32(&clk->src_top2, MUX_GPLL_SEL_MASK);
575 tmp = MUX_CPLL_SEL_MASK | MUX_EPLL_SEL_MASK | MUX_VPLL_SEL_MASK
578 val = readl(&clk->mux_stat_top2);
579 } while ((val | tmp) != val);
581 clrbits_le32(&clk->src_cdrex, MUX_BPLL_SEL_MASK);
583 val = readl(&clk->mux_stat_cdrex);
584 } while ((val | MUX_BPLL_SEL_MASK) != val);
587 writel(mem->apll_pdiv * PLL_LOCK_FACTOR, &clk->apll_lock);
588 writel(mem->mpll_pdiv * PLL_LOCK_FACTOR, &clk->mpll_lock);
589 writel(mem->bpll_pdiv * PLL_LOCK_FACTOR, &clk->bpll_lock);
590 writel(mem->cpll_pdiv * PLL_LOCK_FACTOR, &clk->cpll_lock);
591 writel(mem->gpll_pdiv * PLL_X_LOCK_FACTOR, &clk->gpll_lock);
592 writel(mem->epll_pdiv * PLL_X_LOCK_FACTOR, &clk->epll_lock);
593 writel(mem->vpll_pdiv * PLL_X_LOCK_FACTOR, &clk->vpll_lock);
595 writel(CLK_REG_DISABLE, &clk->pll_div2_sel);
597 writel(MUX_HPM_SEL_MASK, &clk->src_cpu);
599 val = readl(&clk->mux_stat_cpu);
600 } while ((val | HPM_SEL_SCLK_MPLL) != val);
602 val = arm_clk_ratio->arm2_ratio << 28
603 | arm_clk_ratio->apll_ratio << 24
604 | arm_clk_ratio->pclk_dbg_ratio << 20
605 | arm_clk_ratio->atb_ratio << 16
606 | arm_clk_ratio->periph_ratio << 12
607 | arm_clk_ratio->acp_ratio << 8
608 | arm_clk_ratio->cpud_ratio << 4
609 | arm_clk_ratio->arm_ratio;
610 writel(val, &clk->div_cpu0);
612 val = readl(&clk->div_stat_cpu0);
615 writel(CLK_DIV_CPU1_VAL, &clk->div_cpu1);
617 val = readl(&clk->div_stat_cpu1);
621 writel(APLL_CON1_VAL, &clk->apll_con1);
622 val = set_pll(arm_clk_ratio->apll_mdiv, arm_clk_ratio->apll_pdiv,
623 arm_clk_ratio->apll_sdiv);
624 writel(val, &clk->apll_con0);
625 while ((readl(&clk->apll_con0) & APLL_CON0_LOCKED) == 0)
629 writel(MPLL_CON1_VAL, &clk->mpll_con1);
630 val = set_pll(mem->mpll_mdiv, mem->mpll_pdiv, mem->mpll_sdiv);
631 writel(val, &clk->mpll_con0);
632 while ((readl(&clk->mpll_con0) & MPLL_CON0_LOCKED) == 0)
636 writel(BPLL_CON1_VAL, &clk->bpll_con1);
637 val = set_pll(mem->bpll_mdiv, mem->bpll_pdiv, mem->bpll_sdiv);
638 writel(val, &clk->bpll_con0);
639 while ((readl(&clk->bpll_con0) & BPLL_CON0_LOCKED) == 0)
643 writel(CPLL_CON1_VAL, &clk->cpll_con1);
644 val = set_pll(mem->cpll_mdiv, mem->cpll_pdiv, mem->cpll_sdiv);
645 writel(val, &clk->cpll_con0);
646 while ((readl(&clk->cpll_con0) & CPLL_CON0_LOCKED) == 0)
650 writel(GPLL_CON1_VAL, &clk->gpll_con1);
651 val = set_pll(mem->gpll_mdiv, mem->gpll_pdiv, mem->gpll_sdiv);
652 writel(val, &clk->gpll_con0);
653 while ((readl(&clk->gpll_con0) & GPLL_CON0_LOCKED) == 0)
657 writel(EPLL_CON2_VAL, &clk->epll_con2);
658 writel(EPLL_CON1_VAL, &clk->epll_con1);
659 val = set_pll(mem->epll_mdiv, mem->epll_pdiv, mem->epll_sdiv);
660 writel(val, &clk->epll_con0);
661 while ((readl(&clk->epll_con0) & EPLL_CON0_LOCKED) == 0)
665 writel(VPLL_CON2_VAL, &clk->vpll_con2);
666 writel(VPLL_CON1_VAL, &clk->vpll_con1);
667 val = set_pll(mem->vpll_mdiv, mem->vpll_pdiv, mem->vpll_sdiv);
668 writel(val, &clk->vpll_con0);
669 while ((readl(&clk->vpll_con0) & VPLL_CON0_LOCKED) == 0)
672 writel(CLK_SRC_CORE0_VAL, &clk->src_core0);
673 writel(CLK_DIV_CORE0_VAL, &clk->div_core0);
674 while (readl(&clk->div_stat_core0) != 0)
677 writel(CLK_DIV_CORE1_VAL, &clk->div_core1);
678 while (readl(&clk->div_stat_core1) != 0)
681 writel(CLK_DIV_SYSRGT_VAL, &clk->div_sysrgt);
682 while (readl(&clk->div_stat_sysrgt) != 0)
685 writel(CLK_DIV_ACP_VAL, &clk->div_acp);
686 while (readl(&clk->div_stat_acp) != 0)
689 writel(CLK_DIV_SYSLFT_VAL, &clk->div_syslft);
690 while (readl(&clk->div_stat_syslft) != 0)
693 writel(CLK_SRC_TOP0_VAL, &clk->src_top0);
694 writel(CLK_SRC_TOP1_VAL, &clk->src_top1);
695 writel(TOP2_VAL, &clk->src_top2);
696 writel(CLK_SRC_TOP3_VAL, &clk->src_top3);
698 writel(CLK_DIV_TOP0_VAL, &clk->div_top0);
699 while (readl(&clk->div_stat_top0))
702 writel(CLK_DIV_TOP1_VAL, &clk->div_top1);
703 while (readl(&clk->div_stat_top1))
706 writel(CLK_SRC_LEX_VAL, &clk->src_lex);
708 val = readl(&clk->mux_stat_lex);
709 if (val == (val | 1))
713 writel(CLK_DIV_LEX_VAL, &clk->div_lex);
714 while (readl(&clk->div_stat_lex))
717 writel(CLK_DIV_R0X_VAL, &clk->div_r0x);
718 while (readl(&clk->div_stat_r0x))
721 writel(CLK_DIV_R0X_VAL, &clk->div_r0x);
722 while (readl(&clk->div_stat_r0x))
725 writel(CLK_DIV_R1X_VAL, &clk->div_r1x);
726 while (readl(&clk->div_stat_r1x))
729 writel(CLK_REG_DISABLE, &clk->src_cdrex);
731 writel(CLK_DIV_CDREX_VAL, &clk->div_cdrex);
732 while (readl(&clk->div_stat_cdrex))
735 val = readl(&clk->src_cpu);
736 val |= CLK_SRC_CPU_VAL;
737 writel(val, &clk->src_cpu);
739 val = readl(&clk->src_top2);
740 val |= CLK_SRC_TOP2_VAL;
741 writel(val, &clk->src_top2);
743 val = readl(&clk->src_core1);
744 val |= CLK_SRC_CORE1_VAL;
745 writel(val, &clk->src_core1);
747 writel(CLK_SRC_FSYS0_VAL, &clk->src_fsys);
748 writel(CLK_DIV_FSYS0_VAL, &clk->div_fsys0);
749 while (readl(&clk->div_stat_fsys0))
752 writel(CLK_REG_DISABLE, &clk->clkout_cmu_cpu);
753 writel(CLK_REG_DISABLE, &clk->clkout_cmu_core);
754 writel(CLK_REG_DISABLE, &clk->clkout_cmu_acp);
755 writel(CLK_REG_DISABLE, &clk->clkout_cmu_top);
756 writel(CLK_REG_DISABLE, &clk->clkout_cmu_lex);
757 writel(CLK_REG_DISABLE, &clk->clkout_cmu_r0x);
758 writel(CLK_REG_DISABLE, &clk->clkout_cmu_r1x);
759 writel(CLK_REG_DISABLE, &clk->clkout_cmu_cdrex);
761 writel(CLK_SRC_PERIC0_VAL, &clk->src_peric0);
762 writel(CLK_DIV_PERIC0_VAL, &clk->div_peric0);
764 writel(CLK_SRC_PERIC1_VAL, &clk->src_peric1);
765 writel(CLK_DIV_PERIC1_VAL, &clk->div_peric1);
766 writel(CLK_DIV_PERIC2_VAL, &clk->div_peric2);
767 writel(CLK_DIV_PERIC3_VAL, &clk->div_peric3);
769 writel(SCLK_SRC_ISP_VAL, &clk->sclk_src_isp);
770 writel(SCLK_DIV_ISP_VAL, &clk->sclk_div_isp);
771 writel(CLK_DIV_ISP0_VAL, &clk->div_isp0);
772 writel(CLK_DIV_ISP1_VAL, &clk->div_isp1);
773 writel(CLK_DIV_ISP2_VAL, &clk->div_isp2);
775 /* FIMD1 SRC CLK SELECTION */
776 writel(CLK_SRC_DISP1_0_VAL, &clk->src_disp1_0);
778 val = MMC2_PRE_RATIO_VAL << MMC2_PRE_RATIO_OFFSET
779 | MMC2_RATIO_VAL << MMC2_RATIO_OFFSET
780 | MMC3_PRE_RATIO_VAL << MMC3_PRE_RATIO_OFFSET
781 | MMC3_RATIO_VAL << MMC3_RATIO_OFFSET;
782 writel(val, &clk->div_fsys2);
785 static void exynos5420_system_clock_init(void)
787 struct exynos5420_clock *clk =
788 (struct exynos5420_clock *)samsung_get_base_clock();
789 struct mem_timings *mem;
790 struct arm_clk_ratios *arm_clk_ratio;
793 mem = clock_get_mem_timings();
794 arm_clk_ratio = get_arm_ratios();
797 writel(arm_clk_ratio->apll_pdiv * PLL_LOCK_FACTOR, &clk->apll_lock);
798 writel(mem->mpll_pdiv * PLL_LOCK_FACTOR, &clk->mpll_lock);
799 writel(mem->bpll_pdiv * PLL_LOCK_FACTOR, &clk->bpll_lock);
800 writel(mem->cpll_pdiv * PLL_LOCK_FACTOR, &clk->cpll_lock);
801 writel(mem->dpll_pdiv * PLL_LOCK_FACTOR, &clk->dpll_lock);
802 writel(mem->epll_pdiv * PLL_X_LOCK_FACTOR, &clk->epll_lock);
803 writel(mem->vpll_pdiv * PLL_LOCK_FACTOR, &clk->vpll_lock);
804 writel(mem->ipll_pdiv * PLL_LOCK_FACTOR, &clk->ipll_lock);
805 writel(mem->spll_pdiv * PLL_LOCK_FACTOR, &clk->spll_lock);
806 writel(mem->kpll_pdiv * PLL_LOCK_FACTOR, &clk->kpll_lock);
807 writel(mem->rpll_pdiv * PLL_X_LOCK_FACTOR, &clk->rpll_lock);
809 setbits_le32(&clk->src_cpu, MUX_HPM_SEL_MASK);
811 writel(0, &clk->src_top6);
813 writel(0, &clk->src_cdrex);
814 writel(SRC_KFC_HPM_SEL, &clk->src_kfc);
815 writel(HPM_RATIO, &clk->div_cpu1);
816 writel(CLK_DIV_CPU0_VAL, &clk->div_cpu0);
818 /* switch A15 clock source to OSC clock before changing APLL */
819 clrbits_le32(&clk->src_cpu, APLL_FOUT);
822 writel(APLL_CON1_VAL, &clk->apll_con1);
823 val = set_pll(arm_clk_ratio->apll_mdiv,
824 arm_clk_ratio->apll_pdiv,
825 arm_clk_ratio->apll_sdiv);
826 writel(val, &clk->apll_con0);
827 while ((readl(&clk->apll_con0) & PLL_LOCKED) == 0)
830 /* now it is safe to switch to APLL */
831 setbits_le32(&clk->src_cpu, APLL_FOUT);
833 writel(SRC_KFC_HPM_SEL, &clk->src_kfc);
834 writel(CLK_DIV_KFC_VAL, &clk->div_kfc0);
836 /* switch A7 clock source to OSC clock before changing KPLL */
837 clrbits_le32(&clk->src_kfc, KPLL_FOUT);
840 writel(KPLL_CON1_VAL, &clk->kpll_con1);
841 val = set_pll(mem->kpll_mdiv, mem->kpll_pdiv, mem->kpll_sdiv);
842 writel(val, &clk->kpll_con0);
843 while ((readl(&clk->kpll_con0) & PLL_LOCKED) == 0)
846 /* now it is safe to switch to KPLL */
847 setbits_le32(&clk->src_kfc, KPLL_FOUT);
850 writel(MPLL_CON1_VAL, &clk->mpll_con1);
851 val = set_pll(mem->mpll_mdiv, mem->mpll_pdiv, mem->mpll_sdiv);
852 writel(val, &clk->mpll_con0);
853 while ((readl(&clk->mpll_con0) & PLL_LOCKED) == 0)
857 writel(DPLL_CON1_VAL, &clk->dpll_con1);
858 val = set_pll(mem->dpll_mdiv, mem->dpll_pdiv, mem->dpll_sdiv);
859 writel(val, &clk->dpll_con0);
860 while ((readl(&clk->dpll_con0) & PLL_LOCKED) == 0)
864 writel(EPLL_CON2_VAL, &clk->epll_con2);
865 writel(EPLL_CON1_VAL, &clk->epll_con1);
866 val = set_pll(mem->epll_mdiv, mem->epll_pdiv, mem->epll_sdiv);
867 writel(val, &clk->epll_con0);
868 while ((readl(&clk->epll_con0) & PLL_LOCKED) == 0)
872 writel(CPLL_CON1_VAL, &clk->cpll_con1);
873 val = set_pll(mem->cpll_mdiv, mem->cpll_pdiv, mem->cpll_sdiv);
874 writel(val, &clk->cpll_con0);
875 while ((readl(&clk->cpll_con0) & PLL_LOCKED) == 0)
879 writel(IPLL_CON1_VAL, &clk->ipll_con1);
880 val = set_pll(mem->ipll_mdiv, mem->ipll_pdiv, mem->ipll_sdiv);
881 writel(val, &clk->ipll_con0);
882 while ((readl(&clk->ipll_con0) & PLL_LOCKED) == 0)
886 writel(VPLL_CON1_VAL, &clk->vpll_con1);
887 val = set_pll(mem->vpll_mdiv, mem->vpll_pdiv, mem->vpll_sdiv);
888 writel(val, &clk->vpll_con0);
889 while ((readl(&clk->vpll_con0) & PLL_LOCKED) == 0)
893 writel(BPLL_CON1_VAL, &clk->bpll_con1);
894 val = set_pll(mem->bpll_mdiv, mem->bpll_pdiv, mem->bpll_sdiv);
895 writel(val, &clk->bpll_con0);
896 while ((readl(&clk->bpll_con0) & PLL_LOCKED) == 0)
900 writel(SPLL_CON1_VAL, &clk->spll_con1);
901 val = set_pll(mem->spll_mdiv, mem->spll_pdiv, mem->spll_sdiv);
902 writel(val, &clk->spll_con0);
903 while ((readl(&clk->spll_con0) & PLL_LOCKED) == 0)
907 writel(RPLL_CON2_VAL, &clk->rpll_con2);
908 writel(RPLL_CON1_VAL, &clk->rpll_con1);
909 val = set_pll(mem->rpll_mdiv, mem->rpll_pdiv, mem->rpll_sdiv);
910 writel(val, &clk->rpll_con0);
911 while ((readl(&clk->rpll_con0) & PLL_LOCKED) == 0)
914 writel(CLK_DIV_CDREX0_VAL, &clk->div_cdrex0);
915 writel(CLK_DIV_CDREX1_VAL, &clk->div_cdrex1);
917 writel(CLK_SRC_TOP0_VAL, &clk->src_top0);
918 writel(CLK_SRC_TOP1_VAL, &clk->src_top1);
919 writel(CLK_SRC_TOP2_VAL, &clk->src_top2);
920 writel(CLK_SRC_TOP7_VAL, &clk->src_top7);
922 writel(CLK_DIV_TOP0_VAL, &clk->div_top0);
923 writel(CLK_DIV_TOP1_VAL, &clk->div_top1);
924 writel(CLK_DIV_TOP2_VAL, &clk->div_top2);
926 writel(0, &clk->src_top10);
927 writel(0, &clk->src_top11);
928 writel(0, &clk->src_top12);
930 writel(CLK_SRC_TOP3_VAL, &clk->src_top3);
931 writel(CLK_SRC_TOP4_VAL, &clk->src_top4);
932 writel(CLK_SRC_TOP5_VAL, &clk->src_top5);
934 /* DISP1 BLK CLK SELECTION */
935 writel(CLK_SRC_DISP1_0_VAL, &clk->src_disp10);
936 writel(CLK_DIV_DISP1_0_VAL, &clk->div_disp10);
939 writel(AUDIO0_SEL_EPLL, &clk->src_mau);
940 writel(DIV_MAU_VAL, &clk->div_mau);
943 writel(CLK_SRC_FSYS0_VAL, &clk->src_fsys);
944 writel(CLK_DIV_FSYS0_VAL, &clk->div_fsys0);
945 writel(CLK_DIV_FSYS1_VAL, &clk->div_fsys1);
946 writel(CLK_DIV_FSYS2_VAL, &clk->div_fsys2);
948 writel(CLK_SRC_ISP_VAL, &clk->src_isp);
949 writel(CLK_DIV_ISP0_VAL, &clk->div_isp0);
950 writel(CLK_DIV_ISP1_VAL, &clk->div_isp1);
952 writel(CLK_SRC_PERIC0_VAL, &clk->src_peric0);
953 writel(CLK_SRC_PERIC1_VAL, &clk->src_peric1);
955 writel(CLK_DIV_PERIC0_VAL, &clk->div_peric0);
956 writel(CLK_DIV_PERIC1_VAL, &clk->div_peric1);
957 writel(CLK_DIV_PERIC2_VAL, &clk->div_peric2);
958 writel(CLK_DIV_PERIC3_VAL, &clk->div_peric3);
959 writel(CLK_DIV_PERIC4_VAL, &clk->div_peric4);
961 writel(CLK_DIV_CPERI1_VAL, &clk->div_cperi1);
963 writel(CLK_DIV2_RATIO, &clk->clkdiv2_ratio);
964 writel(CLK_DIV4_RATIO, &clk->clkdiv4_ratio);
965 writel(CLK_DIV_G2D, &clk->div_g2d);
967 writel(CLK_SRC_TOP6_VAL, &clk->src_top6);
968 writel(CLK_SRC_CDREX_VAL, &clk->src_cdrex);
969 writel(CLK_SRC_KFC_VAL, &clk->src_kfc);
972 void system_clock_init(void)
974 if (proid_is_exynos5420() || proid_is_exynos5800())
975 exynos5420_system_clock_init();
977 exynos5250_system_clock_init();
980 void clock_init_dp_clock(void)
982 struct exynos5_clock *clk =
983 (struct exynos5_clock *)samsung_get_base_clock();
985 /* DP clock enable */
986 setbits_le32(&clk->gate_ip_disp1, CLK_GATE_DP1_ALLOW);
988 /* We run DP at 267 Mhz */
989 setbits_le32(&clk->div_disp1_0, CLK_DIV_DISP1_0_FIMD1);
993 * Set clock divisor value for booting from EMMC.
994 * Set DWMMC channel-0 clk div to operate mmc0 device at 50MHz.
996 void emmc_boot_clk_div_set(void)
998 struct exynos5_clock *clk =
999 (struct exynos5_clock *)samsung_get_base_clock();
1000 unsigned int div_mmc;
1002 div_mmc = readl((unsigned int) &clk->div_fsys1) & ~FSYS1_MMC0_DIV_MASK;
1003 div_mmc |= FSYS1_MMC0_DIV_VAL;
1004 writel(div_mmc, (unsigned int) &clk->div_fsys1);
projects / karo-tx-uboot.git / blob