arch/arm/cpu/armv7/exynos/power.c

   1 /*
   2  * Copyright (C) 2012 Samsung Electronics
   3  * Donghwa Lee <dh09.lee@samsung.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <asm/io.h>
  10 #include <asm/arch/power.h>
  11
  12 static void exynos4_mipi_phy_control(unsigned int dev_index,
  13                                         unsigned int enable)
  14 {
  15         struct exynos4_power *pmu =
  16             (struct exynos4_power *)samsung_get_base_power();
  17         unsigned int addr, cfg = 0;
  18
  19         if (dev_index == 0)
  20                 addr = (unsigned int)&pmu->mipi_phy0_control;
  21         else
  22                 addr = (unsigned int)&pmu->mipi_phy1_control;
  23
  24
  25         cfg = readl(addr);
  26         if (enable)
  27                 cfg |= (EXYNOS_MIPI_PHY_MRESETN | EXYNOS_MIPI_PHY_ENABLE);
  28         else
  29                 cfg &= ~(EXYNOS_MIPI_PHY_MRESETN | EXYNOS_MIPI_PHY_ENABLE);
  30
  31         writel(cfg, addr);
  32 }
  33
  34 void set_mipi_phy_ctrl(unsigned int dev_index, unsigned int enable)
  35 {
  36         if (cpu_is_exynos4())
  37                 exynos4_mipi_phy_control(dev_index, enable);
  38 }
  39
  40 void exynos5_set_usbhost_phy_ctrl(unsigned int enable)
  41 {
  42         struct exynos5_power *power =
  43                 (struct exynos5_power *)samsung_get_base_power();
  44
  45         if (enable) {
  46                 /* Enabling USBHOST_PHY */
  47                 setbits_le32(&power->usbhost_phy_control,
  48                                 POWER_USB_HOST_PHY_CTRL_EN);
  49         } else {
  50                 /* Disabling USBHOST_PHY */
  51                 clrbits_le32(&power->usbhost_phy_control,
  52                                 POWER_USB_HOST_PHY_CTRL_EN);
  53         }
  54 }
  55
  56 void exynos4412_set_usbhost_phy_ctrl(unsigned int enable)
  57 {
  58         struct exynos4412_power *power =
  59                 (struct exynos4412_power *)samsung_get_base_power();
  60
  61         if (enable) {
  62                 /* Enabling USBHOST_PHY */
  63                 setbits_le32(&power->usbhost_phy_control,
  64                              POWER_USB_HOST_PHY_CTRL_EN);
  65                 setbits_le32(&power->hsic1_phy_control,
  66                              POWER_USB_HOST_PHY_CTRL_EN);
  67                 setbits_le32(&power->hsic2_phy_control,
  68                              POWER_USB_HOST_PHY_CTRL_EN);
  69         } else {
  70                 /* Disabling USBHOST_PHY */
  71                 clrbits_le32(&power->usbhost_phy_control,
  72                              POWER_USB_HOST_PHY_CTRL_EN);
  73                 clrbits_le32(&power->hsic1_phy_control,
  74                              POWER_USB_HOST_PHY_CTRL_EN);
  75                 clrbits_le32(&power->hsic2_phy_control,
  76                              POWER_USB_HOST_PHY_CTRL_EN);
  77         }
  78 }
  79
  80 void set_usbhost_phy_ctrl(unsigned int enable)
  81 {
  82         if (cpu_is_exynos5())
  83                 exynos5_set_usbhost_phy_ctrl(enable);
  84         else if (cpu_is_exynos4())
  85                 if (proid_is_exynos4412())
  86                         exynos4412_set_usbhost_phy_ctrl(enable);
  87 }
  88
  89 static void exynos5_set_usbdrd_phy_ctrl(unsigned int enable)
  90 {
  91         struct exynos5_power *power =
  92                 (struct exynos5_power *)samsung_get_base_power();
  93
  94         if (enable) {
  95                 /* Enabling USBDRD_PHY */
  96                 setbits_le32(&power->usbdrd_phy_control,
  97                                 POWER_USB_DRD_PHY_CTRL_EN);
  98         } else {
  99                 /* Disabling USBDRD_PHY */
 100                 clrbits_le32(&power->usbdrd_phy_control,
 101                                 POWER_USB_DRD_PHY_CTRL_EN);
 102         }
 103 }
 104
 105 void set_usbdrd_phy_ctrl(unsigned int enable)
 106 {
 107         if (cpu_is_exynos5())
 108                 exynos5_set_usbdrd_phy_ctrl(enable);
 109 }
 110
 111 static void exynos5_dp_phy_control(unsigned int enable)
 112 {
 113         unsigned int cfg;
 114         struct exynos5_power *power =
 115             (struct exynos5_power *)samsung_get_base_power();
 116
 117         cfg = readl(&power->dptx_phy_control);
 118         if (enable)
 119                 cfg |= EXYNOS_DP_PHY_ENABLE;
 120         else
 121                 cfg &= ~EXYNOS_DP_PHY_ENABLE;
 122
 123         writel(cfg, &power->dptx_phy_control);
 124 }
 125
 126 void set_dp_phy_ctrl(unsigned int enable)
 127 {
 128         if (cpu_is_exynos5())
 129                 exynos5_dp_phy_control(enable);
 130 }
 131
 132 static void exynos5_set_ps_hold_ctrl(void)
 133 {
 134         struct exynos5_power *power =
 135                 (struct exynos5_power *)samsung_get_base_power();
 136
 137         /* Set PS-Hold high */
 138         setbits_le32(&power->ps_hold_control,
 139                         EXYNOS_PS_HOLD_CONTROL_DATA_HIGH);
 140 }
 141
 142 /*
 143  * Set ps_hold data driving value high
 144  * This enables the machine to stay powered on
 145  * after the initial power-on condition goes away
 146  * (e.g. power button).
 147  */
 148 void set_ps_hold_ctrl(void)
 149 {
 150         if (cpu_is_exynos5())
 151                 exynos5_set_ps_hold_ctrl();
 152 }
 153
 154
 155 static void exynos5_set_xclkout(void)
 156 {
 157         struct exynos5_power *power =
 158                 (struct exynos5_power *)samsung_get_base_power();
 159
 160         /* use xxti for xclk out */
 161         clrsetbits_le32(&power->pmu_debug, PMU_DEBUG_CLKOUT_SEL_MASK,
 162                                 PMU_DEBUG_XXTI);
 163 }
 164
 165 void set_xclkout(void)
 166 {
 167         if (cpu_is_exynos5())
 168                 exynos5_set_xclkout();
 169 }
 170
 171 /* Enables hardware tripping to power off the system when TMU fails */
 172 void set_hw_thermal_trip(void)
 173 {
 174         if (cpu_is_exynos5()) {
 175                 struct exynos5_power *power =
 176                         (struct exynos5_power *)samsung_get_base_power();
 177
 178                 /* PS_HOLD_CONTROL register ENABLE_HW_TRIP bit*/
 179                 setbits_le32(&power->ps_hold_control, POWER_ENABLE_HW_TRIP);
 180         }
 181 }
 182
 183 static uint32_t exynos5_get_reset_status(void)
 184 {
 185         struct exynos5_power *power =
 186                 (struct exynos5_power *)samsung_get_base_power();
 187
 188         return power->inform1;
 189 }
 190
 191 static uint32_t exynos4_get_reset_status(void)
 192 {
 193         struct exynos4_power *power =
 194                 (struct exynos4_power *)samsung_get_base_power();
 195
 196         return power->inform1;
 197 }
 198
 199 uint32_t get_reset_status(void)
 200 {
 201         if (cpu_is_exynos5())
 202                 return exynos5_get_reset_status();
 203         else
 204                 return  exynos4_get_reset_status();
 205 }
 206
 207 static void exynos5_power_exit_wakeup(void)
 208 {
 209         struct exynos5_power *power =
 210                 (struct exynos5_power *)samsung_get_base_power();
 211         typedef void (*resume_func)(void);
 212
 213         ((resume_func)power->inform0)();
 214 }
 215
 216 static void exynos4_power_exit_wakeup(void)
 217 {
 218         struct exynos4_power *power =
 219                 (struct exynos4_power *)samsung_get_base_power();
 220         typedef void (*resume_func)(void);
 221
 222         ((resume_func)power->inform0)();
 223 }
 224
 225 void power_exit_wakeup(void)
 226 {
 227         if (cpu_is_exynos5())
 228                 exynos5_power_exit_wakeup();
 229         else
 230                 exynos4_power_exit_wakeup();
 231 }
 232
 233 unsigned int get_boot_mode(void)
 234 {
 235         unsigned int om_pin = samsung_get_base_power();
 236
 237         return readl(om_pin) & OM_PIN_MASK;
 238 }