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Exynos: Make sure ps_hold gets set in the SPL
[karo-tx-uboot.git] / arch / arm / cpu / armv7 / exynos / power.c
1 /*
2  * Copyright (C) 2012 Samsung Electronics
3  * Donghwa Lee <dh09.lee@samsung.com>
4  *
5  * SPDX-License-Identifier:     GPL-2.0+
6  */
7
8 #include <common.h>
9 #include <asm/io.h>
10 #include <asm/arch/power.h>
11
12 static void exynos4_mipi_phy_control(unsigned int dev_index,
13                                         unsigned int enable)
14 {
15         struct exynos4_power *pmu =
16             (struct exynos4_power *)samsung_get_base_power();
17         unsigned int addr, cfg = 0;
18
19         if (dev_index == 0)
20                 addr = (unsigned int)&pmu->mipi_phy0_control;
21         else
22                 addr = (unsigned int)&pmu->mipi_phy1_control;
23
24
25         cfg = readl(addr);
26         if (enable)
27                 cfg |= (EXYNOS_MIPI_PHY_MRESETN | EXYNOS_MIPI_PHY_ENABLE);
28         else
29                 cfg &= ~(EXYNOS_MIPI_PHY_MRESETN | EXYNOS_MIPI_PHY_ENABLE);
30
31         writel(cfg, addr);
32 }
33
34 void set_mipi_phy_ctrl(unsigned int dev_index, unsigned int enable)
35 {
36         if (cpu_is_exynos4())
37                 exynos4_mipi_phy_control(dev_index, enable);
38 }
39
40 void exynos5_set_usbhost_phy_ctrl(unsigned int enable)
41 {
42         struct exynos5_power *power =
43                 (struct exynos5_power *)samsung_get_base_power();
44
45         if (enable) {
46                 /* Enabling USBHOST_PHY */
47                 setbits_le32(&power->usbhost_phy_control,
48                                 POWER_USB_HOST_PHY_CTRL_EN);
49         } else {
50                 /* Disabling USBHOST_PHY */
51                 clrbits_le32(&power->usbhost_phy_control,
52                                 POWER_USB_HOST_PHY_CTRL_EN);
53         }
54 }
55
56 void set_usbhost_phy_ctrl(unsigned int enable)
57 {
58         if (cpu_is_exynos5())
59                 exynos5_set_usbhost_phy_ctrl(enable);
60 }
61
62 static void exynos5_set_usbdrd_phy_ctrl(unsigned int enable)
63 {
64         struct exynos5_power *power =
65                 (struct exynos5_power *)samsung_get_base_power();
66
67         if (enable) {
68                 /* Enabling USBDRD_PHY */
69                 setbits_le32(&power->usbdrd_phy_control,
70                                 POWER_USB_DRD_PHY_CTRL_EN);
71         } else {
72                 /* Disabling USBDRD_PHY */
73                 clrbits_le32(&power->usbdrd_phy_control,
74                                 POWER_USB_DRD_PHY_CTRL_EN);
75         }
76 }
77
78 void set_usbdrd_phy_ctrl(unsigned int enable)
79 {
80         if (cpu_is_exynos5())
81                 exynos5_set_usbdrd_phy_ctrl(enable);
82 }
83
84 static void exynos5_dp_phy_control(unsigned int enable)
85 {
86         unsigned int cfg;
87         struct exynos5_power *power =
88             (struct exynos5_power *)samsung_get_base_power();
89
90         cfg = readl(&power->dptx_phy_control);
91         if (enable)
92                 cfg |= EXYNOS_DP_PHY_ENABLE;
93         else
94                 cfg &= ~EXYNOS_DP_PHY_ENABLE;
95
96         writel(cfg, &power->dptx_phy_control);
97 }
98
99 void set_dp_phy_ctrl(unsigned int enable)
100 {
101         if (cpu_is_exynos5())
102                 exynos5_dp_phy_control(enable);
103 }
104
105 static void exynos5_set_ps_hold_ctrl(void)
106 {
107         struct exynos5_power *power =
108                 (struct exynos5_power *)samsung_get_base_power();
109
110         /* Set PS-Hold high */
111         setbits_le32(&power->ps_hold_control,
112                         EXYNOS_PS_HOLD_CONTROL_DATA_HIGH);
113 }
114
115 /*
116  * Set ps_hold data driving value high
117  * This enables the machine to stay powered on
118  * after the initial power-on condition goes away
119  * (e.g. power button).
120  */
121 void set_ps_hold_ctrl(void)
122 {
123         if (cpu_is_exynos5())
124                 exynos5_set_ps_hold_ctrl();
125 }
126
127
128 static void exynos5_set_xclkout(void)
129 {
130         struct exynos5_power *power =
131                 (struct exynos5_power *)samsung_get_base_power();
132
133         /* use xxti for xclk out */
134         clrsetbits_le32(&power->pmu_debug, PMU_DEBUG_CLKOUT_SEL_MASK,
135                                 PMU_DEBUG_XXTI);
136 }
137
138 void set_xclkout(void)
139 {
140         if (cpu_is_exynos5())
141                 exynos5_set_xclkout();
142 }
143
144 /* Enables hardware tripping to power off the system when TMU fails */
145 void set_hw_thermal_trip(void)
146 {
147         if (cpu_is_exynos5()) {
148                 struct exynos5_power *power =
149                         (struct exynos5_power *)samsung_get_base_power();
150
151                 /* PS_HOLD_CONTROL register ENABLE_HW_TRIP bit*/
152                 setbits_le32(&power->ps_hold_control, POWER_ENABLE_HW_TRIP);
153         }
154 }
155
156 static uint32_t exynos5_get_reset_status(void)
157 {
158         struct exynos5_power *power =
159                 (struct exynos5_power *)samsung_get_base_power();
160
161         return power->inform1;
162 }
163
164 static uint32_t exynos4_get_reset_status(void)
165 {
166         struct exynos4_power *power =
167                 (struct exynos4_power *)samsung_get_base_power();
168
169         return power->inform1;
170 }
171
172 uint32_t get_reset_status(void)
173 {
174         if (cpu_is_exynos5())
175                 return exynos5_get_reset_status();
176         else
177                 return  exynos4_get_reset_status();
178 }
179
180 static void exynos5_power_exit_wakeup(void)
181 {
182         struct exynos5_power *power =
183                 (struct exynos5_power *)samsung_get_base_power();
184         typedef void (*resume_func)(void);
185
186         ((resume_func)power->inform0)();
187 }
188
189 static void exynos4_power_exit_wakeup(void)
190 {
191         struct exynos4_power *power =
192                 (struct exynos4_power *)samsung_get_base_power();
193         typedef void (*resume_func)(void);
194
195         ((resume_func)power->inform0)();
196 }
197
198 void power_exit_wakeup(void)
199 {
200         if (cpu_is_exynos5())
201                 exynos5_power_exit_wakeup();
202         else
203                 exynos4_power_exit_wakeup();
204 }