arch/arm/cpu/armv7/exynos/system.c

   1 /*
   2  * Copyright (C) 2012 Samsung Electronics
   3  * Donghwa Lee <dh09.lee@samsung.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <asm/io.h>
  10 #include <asm/arch/system.h>
  11
  12 static void exynos5_set_usbhost_mode(unsigned int mode)
  13 {
  14         struct exynos5_sysreg *sysreg =
  15                 (struct exynos5_sysreg *)samsung_get_base_sysreg();
  16
  17         /* Setting USB20PHY_CONFIG register to USB 2.0 HOST link */
  18         if (mode == USB20_PHY_CFG_HOST_LINK_EN) {
  19                 setbits_le32(&sysreg->usb20phy_cfg,
  20                                 USB20_PHY_CFG_HOST_LINK_EN);
  21         } else {
  22                 clrbits_le32(&sysreg->usb20phy_cfg,
  23                                 USB20_PHY_CFG_HOST_LINK_EN);
  24         }
  25 }
  26
  27 void set_usbhost_mode(unsigned int mode)
  28 {
  29         if (cpu_is_exynos5())
  30                 exynos5_set_usbhost_mode(mode);
  31 }
  32
  33 static void exynos4_set_system_display(void)
  34 {
  35         struct exynos4_sysreg *sysreg =
  36             (struct exynos4_sysreg *)samsung_get_base_sysreg();
  37         unsigned int cfg = 0;
  38
  39         /*
  40          * system register path set
  41          * 0: MIE/MDNIE
  42          * 1: FIMD Bypass
  43          */
  44         cfg = readl(&sysreg->display_ctrl);
  45         cfg |= (1 << 1);
  46         writel(cfg, &sysreg->display_ctrl);
  47 }
  48
  49 static void exynos5_set_system_display(void)
  50 {
  51         struct exynos5_sysreg *sysreg =
  52             (struct exynos5_sysreg *)samsung_get_base_sysreg();
  53         unsigned int cfg = 0;
  54
  55         /*
  56          * system register path set
  57          * 0: MIE/MDNIE
  58          * 1: FIMD Bypass
  59          */
  60         cfg = readl(&sysreg->disp1blk_cfg);
  61         cfg |= (1 << 15);
  62         writel(cfg, &sysreg->disp1blk_cfg);
  63 }
  64
  65 void set_system_display_ctrl(void)
  66 {
  67         if (cpu_is_exynos4())
  68                 exynos4_set_system_display();
  69         else
  70                 exynos5_set_system_display();
  71 }