3 * Sascha Hauer, Pengutronix
5 * (C) Copyright 2009 Freescale Semiconductor, Inc.
7 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/errno.h>
13 #include <asm/arch/imx-regs.h>
14 #include <asm/arch/crm_regs.h>
15 #include <asm/arch/clock.h>
17 #include <asm/arch/sys_proto.h>
29 struct mxc_pll_reg *mxc_plls[PLL_CLOCKS] = {
30 [PLL1_CLOCK] = (struct mxc_pll_reg *)PLL1_BASE_ADDR,
31 [PLL2_CLOCK] = (struct mxc_pll_reg *)PLL2_BASE_ADDR,
32 [PLL3_CLOCK] = (struct mxc_pll_reg *)PLL3_BASE_ADDR,
34 [PLL4_CLOCK] = (struct mxc_pll_reg *)PLL4_BASE_ADDR,
38 #define AHB_CLK_ROOT 133333333
39 #define SZ_DEC_1M 1000000
40 #define PLL_PD_MAX 16 /* Actual pd+1 */
41 #define PLL_MFI_MAX 15
49 #define MXC_IPG_PER_CLK MXC_IPG_PERCLK
51 struct fixed_pll_mfd {
56 static const struct fixed_pll_mfd fixed_mfd[] = {
67 #define PLL_FREQ_MAX(ref_clk) (4 * (ref_clk) * PLL_MFI_MAX)
68 #define PLL_FREQ_MIN(ref_clk) \
69 ((4 * (ref_clk) * PLL_MFI_MIN) / PLL_PD_MAX)
70 #define MAX_DDR_CLK 420000000
71 #define NFC_CLK_MAX 34000000
73 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
75 int clk_enable(struct clk *clk)
82 if (clk->usecount++ == 0) {
85 ret = clk->enable(clk);
92 void clk_disable(struct clk *clk)
97 if (!(--clk->usecount)) {
101 if (clk->usecount < 0) {
102 printf("%s: clk %p (%s) underflow\n", __func__, clk, clk->name);
107 int clk_get_usecount(struct clk *clk)
112 return clk->usecount;
115 u32 clk_get_rate(struct clk *clk)
123 struct clk *clk_get_parent(struct clk *clk)
131 int clk_set_rate(struct clk *clk, unsigned long rate)
133 if (clk && clk->set_rate)
134 clk->set_rate(clk, rate);
138 long clk_round_rate(struct clk *clk, unsigned long rate)
140 if (clk == NULL || !clk->round_rate)
143 return clk->round_rate(clk, rate);
146 int clk_set_parent(struct clk *clk, struct clk *parent)
148 debug("Setting parent of clk %p to %p (%p)\n", clk, parent,
149 clk ? clk->parent : NULL);
151 if (!clk || clk == parent)
154 if (clk->set_parent) {
157 ret = clk->set_parent(clk, parent);
161 clk->parent = parent;
165 void set_usboh3_clk(void)
167 clrsetbits_le32(&mxc_ccm->cscmr1,
168 MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK,
169 MXC_CCM_CSCMR1_USBOH3_CLK_SEL(1));
170 clrsetbits_le32(&mxc_ccm->cscdr1,
171 MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK |
172 MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK,
173 MXC_CCM_CSCDR1_USBOH3_CLK_PRED(4) |
174 MXC_CCM_CSCDR1_USBOH3_CLK_PODF(1));
177 void enable_usboh3_clk(bool enable)
179 unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
181 clrsetbits_le32(&mxc_ccm->CCGR2,
182 MXC_CCM_CCGR2_USBOH3_60M(MXC_CCM_CCGR_CG_MASK),
183 MXC_CCM_CCGR2_USBOH3_60M(cg));
186 void ipu_clk_enable(void)
188 /* IPU root clock derived from AXI B */
189 clrsetbits_le32(&mxc_ccm->cbcmr, MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK,
190 MXC_CCM_CBCMR_IPU_HSP_CLK_SEL(1));
192 setbits_le32(&mxc_ccm->CCGR5,
193 MXC_CCM_CCGR5_IPU(MXC_CCM_CCGR_CG_MASK));
195 /* Handshake with IPU when certain clock rates are changed. */
196 clrbits_le32(&mxc_ccm->ccdr, MXC_CCM_CCDR_IPU_HS_MASK);
198 /* Handshake with IPU when LPM is entered as its enabled. */
199 clrbits_le32(&mxc_ccm->clpcr, MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS);
202 void ipu_clk_disable(void)
204 clrbits_le32(&mxc_ccm->CCGR5,
205 MXC_CCM_CCGR5_IPU(MXC_CCM_CCGR_CG_MASK));
207 /* Handshake with IPU when certain clock rates are changed. */
208 setbits_le32(&mxc_ccm->ccdr, MXC_CCM_CCDR_IPU_HS_MASK);
210 /* Handshake with IPU when LPM is entered as its enabled. */
211 setbits_le32(&mxc_ccm->clpcr, MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS);
214 void ipu_di_clk_enable(int di)
218 setbits_le32(&mxc_ccm->CCGR6,
219 MXC_CCM_CCGR6_IPU_DI0(MXC_CCM_CCGR_CG_MASK));
222 setbits_le32(&mxc_ccm->CCGR6,
223 MXC_CCM_CCGR6_IPU_DI1(MXC_CCM_CCGR_CG_MASK));
226 printf("%s: Invalid DI index %d\n", __func__, di);
230 void ipu_di_clk_disable(int di)
234 clrbits_le32(&mxc_ccm->CCGR6,
235 MXC_CCM_CCGR6_IPU_DI0(MXC_CCM_CCGR_CG_MASK));
238 clrbits_le32(&mxc_ccm->CCGR6,
239 MXC_CCM_CCGR6_IPU_DI1(MXC_CCM_CCGR_CG_MASK));
242 printf("%s: Invalid DI index %d\n", __func__, di);
247 void ldb_clk_enable(int ldb)
251 setbits_le32(&mxc_ccm->CCGR6,
252 MXC_CCM_CCGR6_LDB_DI0(MXC_CCM_CCGR_CG_MASK));
255 setbits_le32(&mxc_ccm->CCGR6,
256 MXC_CCM_CCGR6_LDB_DI1(MXC_CCM_CCGR_CG_MASK));
259 printf("%s: Invalid LDB index %d\n", __func__, ldb);
263 void ldb_clk_disable(int ldb)
267 clrbits_le32(&mxc_ccm->CCGR6,
268 MXC_CCM_CCGR6_LDB_DI0(MXC_CCM_CCGR_CG_MASK));
271 clrbits_le32(&mxc_ccm->CCGR6,
272 MXC_CCM_CCGR6_LDB_DI1(MXC_CCM_CCGR_CG_MASK));
275 printf("%s: Invalid LDB index %d\n", __func__, ldb);
280 #ifdef CONFIG_SYS_I2C_MXC
281 /* i2c_num can be from 0, to 1 for i.MX51 and 2 for i.MX53 */
282 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
286 #if defined(CONFIG_MX51)
288 #elif defined(CONFIG_MX53)
292 mask = MXC_CCM_CCGR_CG_MASK <<
293 (MXC_CCM_CCGR1_I2C1_OFFSET + (i2c_num << 1));
295 setbits_le32(&mxc_ccm->CCGR1, mask);
297 clrbits_le32(&mxc_ccm->CCGR1, mask);
302 void set_usb_phy_clk(void)
304 clrbits_le32(&mxc_ccm->cscmr1, MXC_CCM_CSCMR1_USB_PHY_CLK_SEL);
307 #if defined(CONFIG_MX51)
308 void enable_usb_phy1_clk(bool enable)
310 unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
312 clrsetbits_le32(&mxc_ccm->CCGR2,
313 MXC_CCM_CCGR2_USB_PHY(MXC_CCM_CCGR_CG_MASK),
314 MXC_CCM_CCGR2_USB_PHY(cg));
317 void enable_usb_phy2_clk(bool enable)
319 /* i.MX51 has a single USB PHY clock, so do nothing here. */
321 #elif defined(CONFIG_MX53)
322 void enable_usb_phy1_clk(bool enable)
324 unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
326 clrsetbits_le32(&mxc_ccm->CCGR4,
327 MXC_CCM_CCGR4_USB_PHY1(MXC_CCM_CCGR_CG_MASK),
328 MXC_CCM_CCGR4_USB_PHY1(cg));
331 void enable_usb_phy2_clk(bool enable)
333 unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
335 clrsetbits_le32(&mxc_ccm->CCGR4,
336 MXC_CCM_CCGR4_USB_PHY2(MXC_CCM_CCGR_CG_MASK),
337 MXC_CCM_CCGR4_USB_PHY2(cg));
342 * Calculate the frequency of PLLn.
344 static uint32_t decode_pll(struct mxc_pll_reg *pll, uint32_t infreq)
347 int mfd, mfn, mfi, pdf, ret;
348 uint64_t refclk, temp;
351 ctrl = readl(&pll->ctrl);
353 if (ctrl & MXC_DPLLC_CTL_HFSM) {
354 mfn = readl(&pll->hfs_mfn);
355 mfd = readl(&pll->hfs_mfd);
356 op = readl(&pll->hfs_op);
358 mfn = readl(&pll->mfn);
359 mfd = readl(&pll->mfd);
360 op = readl(&pll->op);
363 mfd &= MXC_DPLLC_MFD_MFD_MASK;
364 mfn &= MXC_DPLLC_MFN_MFN_MASK;
365 pdf = op & MXC_DPLLC_OP_PDF_MASK;
366 mfi = MXC_DPLLC_OP_MFI_RD(op);
373 if (mfn >= 0x04000000) {
380 if (ctrl & MXC_DPLLC_CTL_DPDCK0_2_EN)
383 temp = refclk * mfn_abs;
384 do_div(temp, mfd + 1);
398 * This function returns the Frequency Pre-Multiplier clock.
400 static u32 get_fpm(void)
403 u32 ccr = readl(&mxc_ccm->ccr);
405 if (ccr & MXC_CCM_CCR_FPM_MULT)
410 return MXC_CLK32 * mult;
415 * This function returns the low power audio clock.
417 static u32 get_lp_apm(void)
420 u32 ccsr = readl(&mxc_ccm->ccsr);
422 if (ccsr & MXC_CCM_CCSR_LP_APM)
423 #if defined(CONFIG_MX51)
425 #elif defined(CONFIG_MX53)
426 ret_val = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK);
437 u32 get_mcu_main_clk(void)
441 reg = MXC_CCM_CACRR_ARM_PODF_RD(readl(&mxc_ccm->cacrr));
442 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
443 return freq / (reg + 1);
447 * Get the rate of peripheral's root clock.
449 u32 get_periph_clk(void)
453 reg = readl(&mxc_ccm->cbcdr);
454 if (!(reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL))
455 return decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK);
456 reg = readl(&mxc_ccm->cbcmr);
457 switch (MXC_CCM_CBCMR_PERIPH_CLK_SEL_RD(reg)) {
459 return decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
461 return decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK);
471 * Get the rate of ipg clock.
473 static u32 get_ipg_clk(void)
475 uint32_t freq, reg, div;
477 freq = get_ahb_clk();
479 reg = readl(&mxc_ccm->cbcdr);
480 div = MXC_CCM_CBCDR_IPG_PODF_RD(reg) + 1;
486 * Get the rate of ipg_per clock.
488 static u32 get_ipg_per_clk(void)
490 u32 freq, pred1, pred2, podf;
492 if (readl(&mxc_ccm->cbcmr) & MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL)
493 return get_ipg_clk();
495 if (readl(&mxc_ccm->cbcmr) & MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL)
498 freq = get_periph_clk();
499 podf = readl(&mxc_ccm->cbcdr);
500 pred1 = MXC_CCM_CBCDR_PERCLK_PRED1_RD(podf);
501 pred2 = MXC_CCM_CBCDR_PERCLK_PRED2_RD(podf);
502 podf = MXC_CCM_CBCDR_PERCLK_PODF_RD(podf);
503 return freq / ((pred1 + 1) * (pred2 + 1) * (podf + 1));
506 /* Get the output clock rate of a standard PLL MUX for peripherals. */
507 static u32 get_standard_pll_sel_clk(u32 clk_sel)
511 switch (clk_sel & 0x3) {
513 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
516 freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK);
519 freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK);
530 * Get the rate of uart clk.
532 static u32 get_uart_clk(void)
534 unsigned int clk_sel, freq, reg, pred, podf;
536 reg = readl(&mxc_ccm->cscmr1);
537 clk_sel = MXC_CCM_CSCMR1_UART_CLK_SEL_RD(reg);
538 freq = get_standard_pll_sel_clk(clk_sel);
540 reg = readl(&mxc_ccm->cscdr1);
541 pred = MXC_CCM_CSCDR1_UART_CLK_PRED_RD(reg);
542 podf = MXC_CCM_CSCDR1_UART_CLK_PODF_RD(reg);
543 freq /= (pred + 1) * (podf + 1);
549 * get cspi clock rate.
551 static u32 imx_get_cspiclk(void)
553 u32 ret_val = 0, pdf, pre_pdf, clk_sel, freq;
554 u32 cscmr1 = readl(&mxc_ccm->cscmr1);
555 u32 cscdr2 = readl(&mxc_ccm->cscdr2);
557 pre_pdf = MXC_CCM_CSCDR2_CSPI_CLK_PRED_RD(cscdr2);
558 pdf = MXC_CCM_CSCDR2_CSPI_CLK_PODF_RD(cscdr2);
559 clk_sel = MXC_CCM_CSCMR1_CSPI_CLK_SEL_RD(cscmr1);
560 freq = get_standard_pll_sel_clk(clk_sel);
561 ret_val = freq / ((pre_pdf + 1) * (pdf + 1));
566 * get esdhc clock rate.
568 static u32 get_esdhc_clk(u32 port)
570 u32 clk_sel = 0, pred = 0, podf = 0, freq = 0;
571 u32 cscmr1 = readl(&mxc_ccm->cscmr1);
572 u32 cscdr1 = readl(&mxc_ccm->cscdr1);
576 clk_sel = MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_RD(cscmr1);
577 pred = MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_RD(cscdr1);
578 podf = MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_RD(cscdr1);
581 clk_sel = MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_RD(cscmr1);
582 pred = MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_RD(cscdr1);
583 podf = MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_RD(cscdr1);
586 if (cscmr1 & MXC_CCM_CSCMR1_ESDHC3_CLK_SEL)
587 return get_esdhc_clk(1);
589 return get_esdhc_clk(0);
591 if (cscmr1 & MXC_CCM_CSCMR1_ESDHC4_CLK_SEL)
592 return get_esdhc_clk(1);
594 return get_esdhc_clk(0);
599 freq = get_standard_pll_sel_clk(clk_sel) / ((pred + 1) * (podf + 1));
603 static u32 get_axi_a_clk(void)
605 u32 cbcdr = readl(&mxc_ccm->cbcdr);
606 u32 pdf = MXC_CCM_CBCDR_AXI_A_PODF_RD(cbcdr);
608 return get_periph_clk() / (pdf + 1);
611 static u32 get_axi_b_clk(void)
613 u32 cbcdr = readl(&mxc_ccm->cbcdr);
614 u32 pdf = MXC_CCM_CBCDR_AXI_B_PODF_RD(cbcdr);
616 return get_periph_clk() / (pdf + 1);
619 static u32 get_emi_slow_clk(void)
621 u32 cbcdr = readl(&mxc_ccm->cbcdr);
622 u32 emi_clk_sel = cbcdr & MXC_CCM_CBCDR_EMI_CLK_SEL;
623 u32 pdf = MXC_CCM_CBCDR_EMI_PODF_RD(cbcdr);
626 return get_ahb_clk() / (pdf + 1);
628 return get_periph_clk() / (pdf + 1);
631 static u32 get_nfc_clk(void)
633 u32 parent_rate = get_emi_slow_clk();
634 u32 div = readl(&mxc_ccm->cbcdr);
636 div &= MXC_CCM_CBCDR_NFC_PODF_MASK;
637 div >>= MXC_CCM_CBCDR_NFC_PODF_OFFSET;
639 return parent_rate / div;
642 static u32 get_ddr_clk(void)
645 u32 cbcmr = readl(&mxc_ccm->cbcmr);
646 u32 ddr_clk_sel = MXC_CCM_CBCMR_DDR_CLK_SEL_RD(cbcmr);
648 u32 cbcdr = readl(&mxc_ccm->cbcdr);
649 if (cbcdr & MXC_CCM_CBCDR_DDR_HIFREQ_SEL) {
650 u32 ddr_clk_podf = MXC_CCM_CBCDR_DDR_PODF_RD(cbcdr);
652 ret_val = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
653 ret_val /= ddr_clk_podf + 1;
658 switch (ddr_clk_sel) {
660 ret_val = get_axi_a_clk();
663 ret_val = get_axi_b_clk();
666 ret_val = get_emi_slow_clk();
669 ret_val = get_ahb_clk();
679 * The API of get mxc clocks.
681 unsigned int mxc_get_clock(enum mxc_clock clk)
685 return get_mcu_main_clk();
687 return get_ahb_clk();
689 return get_ipg_clk();
692 return get_ipg_per_clk();
694 return get_uart_clk();
696 return imx_get_cspiclk();
698 return get_esdhc_clk(0);
700 return get_esdhc_clk(1);
702 return get_esdhc_clk(2);
704 return get_esdhc_clk(3);
706 return get_ipg_clk();
708 return get_ahb_clk();
710 return get_ddr_clk();
712 return get_axi_a_clk();
714 return get_axi_b_clk();
715 case MXC_EMI_SLOW_CLK:
716 return get_emi_slow_clk();
718 return get_nfc_clk();
725 u32 imx_get_uartclk(void)
727 return get_uart_clk();
730 u32 imx_get_fecclk(void)
732 return get_ipg_clk();
735 static int gcd(int m, int n)
750 * This is to calculate various parameters based on reference clock and
751 * targeted clock based on the equation:
752 * t_clk = 2*ref_freq*(mfi + mfn/(mfd+1))/(pd+1)
753 * This calculation is based on a fixed MFD value for simplicity.
755 static int calc_pll_params(u32 ref, u32 target, struct pll_param *pll)
757 int pd, mfi = 1, mfn, mfd;
762 * Make sure targeted freq is in the valid range.
763 * Otherwise the following calculation might be wrong!!!
765 if (target < PLL_FREQ_MIN(ref) ||
766 target > PLL_FREQ_MAX(ref)) {
767 printf("Targeted pll clock should be within [%d - %d]\n",
768 PLL_FREQ_MIN(ref) / SZ_DEC_1M,
769 PLL_FREQ_MAX(ref) / SZ_DEC_1M);
773 for (i = 0; i < ARRAY_SIZE(fixed_mfd); i++) {
774 if (fixed_mfd[i].ref_clk_hz == ref) {
775 mfd = fixed_mfd[i].mfd;
780 if (i == ARRAY_SIZE(fixed_mfd))
783 for (pd = 1; pd <= PLL_PD_MAX; pd++) {
784 t1 = (u64)target * pd;
785 do_div(t1, (4 * ref));
787 if (mfi > PLL_MFI_MAX)
794 * Now got pd and mfi already
796 * mfn = (((target * pd) / 4 - ref * mfi) * mfd) / ref;
798 t1 = (u64)target * pd;
800 t1 = (t1 - ref * mfi) * mfd;
810 debug("ref=%d, target=%d, pd=%d, mfi=%d, mfn=%d, mfd=%d\n",
811 ref, target, pd, mfi, mfn, mfd);
820 #define calc_div(tgt_clk, src_clk, limit) ({ \
822 if (((src_clk) % (tgt_clk)) <= 100) \
823 v = (src_clk) / (tgt_clk); \
825 v = ((src_clk) / (tgt_clk)) + 1;\
831 #define CHANGE_PLL_SETTINGS(pll, pd, fi, fn, fd) \
833 __raw_writel(0x1232, &pll->ctrl); \
834 __raw_writel(0x2, &pll->config); \
835 __raw_writel((((pd) - 1) << 0) | ((fi) << 4), \
837 __raw_writel(fn, &(pll->mfn)); \
838 __raw_writel((fd) - 1, &pll->mfd); \
839 __raw_writel((((pd) - 1) << 0) | ((fi) << 4), \
841 __raw_writel(fn, &pll->hfs_mfn); \
842 __raw_writel((fd) - 1, &pll->hfs_mfd); \
843 __raw_writel(0x1232, &pll->ctrl); \
844 while (!__raw_readl(&pll->ctrl) & 0x1) \
848 static int config_pll_clk(enum pll_clocks index, struct pll_param *pll_param)
850 u32 ccsr = __raw_readl(&mxc_ccm->ccsr);
851 struct mxc_pll_reg *pll = mxc_plls[index];
855 /* Switch ARM to PLL2 clock */
856 __raw_writel(ccsr | 0x4, &mxc_ccm->ccsr);
857 CHANGE_PLL_SETTINGS(pll, pll_param->pd,
858 pll_param->mfi, pll_param->mfn,
861 __raw_writel(ccsr & ~0x4, &mxc_ccm->ccsr);
864 /* Switch to pll2 bypass clock */
865 __raw_writel(ccsr | 0x2, &mxc_ccm->ccsr);
866 CHANGE_PLL_SETTINGS(pll, pll_param->pd,
867 pll_param->mfi, pll_param->mfn,
870 __raw_writel(ccsr & ~0x2, &mxc_ccm->ccsr);
873 /* Switch to pll3 bypass clock */
874 __raw_writel(ccsr | 0x1, &mxc_ccm->ccsr);
875 CHANGE_PLL_SETTINGS(pll, pll_param->pd,
876 pll_param->mfi, pll_param->mfn,
879 __raw_writel(ccsr & ~0x1, &mxc_ccm->ccsr);
883 /* Switch to pll4 bypass clock */
884 __raw_writel(ccsr | 0x20, &mxc_ccm->ccsr);
885 CHANGE_PLL_SETTINGS(pll, pll_param->pd,
886 pll_param->mfi, pll_param->mfn,
889 __raw_writel(ccsr & ~0x20, &mxc_ccm->ccsr);
899 static int __adjust_core_voltage_stub(u32 freq)
903 int adjust_core_voltage(u32 freq)
904 __attribute__((weak, alias("__adjust_core_voltage_stub")));
906 /* Config CPU clock */
907 static int config_core_clk(u32 ref, u32 freq)
910 struct pll_param pll_param;
911 u32 cur_freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
913 if (freq == cur_freq)
916 memset(&pll_param, 0, sizeof(struct pll_param));
918 /* The case that periph uses PLL1 is not considered here */
919 ret = calc_pll_params(ref, freq, &pll_param);
921 printf("Error: Can't find pll parameters for %u.%03uMHz ref %u.%03uMHz\n",
922 freq / 1000000, freq / 1000 % 1000,
923 ref / 1000000, ref / 1000 % 1000);
926 if (freq > cur_freq) {
927 ret = adjust_core_voltage(freq);
929 printf("Failed to adjust core voltage for changing ARM clk from %u.%03uMHz to %u.%03uMHz\n",
930 cur_freq / 1000000, cur_freq / 1000 % 1000,
931 freq / 1000000, freq / 1000 % 1000);
934 ret = config_pll_clk(PLL1_CLOCK, &pll_param);
936 adjust_core_voltage(cur_freq);
939 ret = config_pll_clk(PLL1_CLOCK, &pll_param);
943 ret = adjust_core_voltage(freq);
945 printf("Failed to adjust core voltage for changing ARM clk from %u.%03uMHz to %u.%03uMHz\n",
946 cur_freq / 1000000, cur_freq / 1000 % 1000,
947 freq / 1000000, freq / 1000 % 1000);
948 calc_pll_params(ref, cur_freq, &pll_param);
949 config_pll_clk(PLL1_CLOCK, &pll_param);
955 static int config_nfc_clk(u32 nfc_clk)
957 u32 parent_rate = get_emi_slow_clk();
962 div = parent_rate / nfc_clk;
965 if (parent_rate / div > NFC_CLK_MAX)
967 clrsetbits_le32(&mxc_ccm->cbcdr,
968 MXC_CCM_CBCDR_NFC_PODF_MASK,
969 MXC_CCM_CBCDR_NFC_PODF(div - 1));
970 while (readl(&mxc_ccm->cdhipr) != 0)
975 void enable_nfc_clk(unsigned char enable)
977 unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
979 clrsetbits_le32(&mxc_ccm->CCGR5,
980 MXC_CCM_CCGR5_EMI_ENFC(MXC_CCM_CCGR_CG_MASK),
981 MXC_CCM_CCGR5_EMI_ENFC(cg));
984 #ifdef CONFIG_FSL_IIM
985 void enable_efuse_prog_supply(bool enable)
988 setbits_le32(&mxc_ccm->cgpr,
989 MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE);
991 clrbits_le32(&mxc_ccm->cgpr,
992 MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE);
996 /* Config main_bus_clock for periphs */
997 static int config_periph_clk(u32 ref, u32 freq)
1000 struct pll_param pll_param;
1002 memset(&pll_param, 0, sizeof(struct pll_param));
1004 if (readl(&mxc_ccm->cbcdr) & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
1005 ret = calc_pll_params(ref, freq, &pll_param);
1007 printf("Error:Can't find pll parameters: %d\n",
1011 switch (MXC_CCM_CBCMR_PERIPH_CLK_SEL_RD(
1012 readl(&mxc_ccm->cbcmr))) {
1014 return config_pll_clk(PLL1_CLOCK, &pll_param);
1017 return config_pll_clk(PLL3_CLOCK, &pll_param);
1027 static int config_ddr_clk(u32 emi_clk)
1030 s32 shift = 0, clk_sel, div = 1;
1031 u32 cbcmr = readl(&mxc_ccm->cbcmr);
1033 if (emi_clk > MAX_DDR_CLK) {
1034 printf("Warning:DDR clock should not exceed %d MHz\n",
1035 MAX_DDR_CLK / SZ_DEC_1M);
1036 emi_clk = MAX_DDR_CLK;
1039 clk_src = get_periph_clk();
1040 /* Find DDR clock input */
1041 clk_sel = MXC_CCM_CBCMR_DDR_CLK_SEL_RD(cbcmr);
1059 if ((clk_src % emi_clk) < 10000000)
1060 div = clk_src / emi_clk;
1062 div = (clk_src / emi_clk) + 1;
1066 clrsetbits_le32(&mxc_ccm->cbcdr, 0x7 << shift, (div - 1) << shift);
1067 while (readl(&mxc_ccm->cdhipr) != 0)
1069 writel(0x0, &mxc_ccm->ccdr);
1075 * This function assumes the expected core clock has to be changed by
1076 * modifying the PLL. This is NOT true always but for most of the times,
1077 * it is. So it assumes the PLL output freq is the same as the expected
1078 * core clock (presc=1) unless the core clock is less than PLL_FREQ_MIN.
1079 * In the latter case, it will try to increase the presc value until
1080 * (presc*core_clk) is greater than PLL_FREQ_MIN. It then makes call to
1081 * calc_pll_params() and obtains the values of PD, MFI,MFN, MFD based
1082 * on the targeted PLL and reference input clock to the PLL. Lastly,
1083 * it sets the register based on these values along with the dividers.
1084 * Note 1) There is no value checking for the passed-in divider values
1085 * so the caller has to make sure those values are sensible.
1086 * 2) Also adjust the NFC divider such that the NFC clock doesn't
1087 * exceed NFC_CLK_MAX.
1088 * 3) IPU HSP clock is independent of AHB clock. Even it can go up to
1089 * 177MHz for higher voltage, this function fixes the max to 133MHz.
1090 * 4) This function should not have allowed diag_printf() calls since
1091 * the serial driver has been stoped. But leave then here to allow
1092 * easy debugging by NOT calling the cyg_hal_plf_serial_stop().
1094 int mxc_set_clock(u32 ref, u32 freq, enum mxc_clock clk)
1100 if (config_core_clk(ref, freq))
1103 case MXC_PERIPH_CLK:
1104 if (config_periph_clk(ref, freq))
1108 if (config_ddr_clk(freq))
1112 if (config_nfc_clk(freq))
1116 printf("Warning:Unsupported or invalid clock type\n");
1124 * The clock for the external interface can be set to use internal clock
1125 * if fuse bank 4, row 3, bit 2 is set.
1126 * This is an undocumented feature and it was confirmed by Freescale's support:
1127 * Fuses (but not pins) may be used to configure SATA clocks.
1128 * Particularly the i.MX53 Fuse_Map contains the next information
1129 * about configuring SATA clocks : SATA_ALT_REF_CLK[1:0] (offset 0x180C)
1130 * '00' - 100MHz (External)
1131 * '01' - 50MHz (External)
1132 * '10' - 120MHz, internal (USB PHY)
1135 void mxc_set_sata_internal_clock(void)
1138 (u32 *)(IIM_BASE_ADDR + 0x180c);
1142 clrsetbits_le32(tmp_base, 0x6, 0x4);
1147 * Dump some core clockes.
1149 #define pr_clk_val(c, v) { \
1150 printf("%-11s %3lu.%03lu MHz\n", #c, \
1151 (v) / 1000000, (v) / 1000 % 1000); \
1154 #define pr_clk(c) { \
1155 unsigned long __clk = mxc_get_clock(MXC_##c##_CLK); \
1156 pr_clk_val(c, __clk); \
1159 static int do_mx5_showclocks(void)
1163 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
1164 pr_clk_val(PLL1, freq);
1165 freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK);
1166 pr_clk_val(PLL2, freq);
1167 freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK);
1168 pr_clk_val(PLL3, freq);
1170 freq = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK);
1171 pr_clk_val(PLL4, freq);
1183 #ifdef CONFIG_MXC_SPI
1189 static struct clk_lookup {
1192 } mx5_clk_lookup[] = {
1193 { "arm", MXC_ARM_CLK, },
1196 int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
1200 unsigned long ref = ~0UL;
1203 do_mx5_showclocks();
1204 return CMD_RET_SUCCESS;
1205 } else if (argc == 2 || argc > 4) {
1206 return CMD_RET_USAGE;
1209 freq = simple_strtoul(argv[2], NULL, 0);
1211 printf("Invalid clock frequency %lu\n", freq);
1212 return CMD_RET_FAILURE;
1215 ref = simple_strtoul(argv[3], NULL, 0);
1217 for (i = 0; i < ARRAY_SIZE(mx5_clk_lookup); i++) {
1218 if (strcasecmp(argv[1], mx5_clk_lookup[i].name) == 0) {
1219 switch (mx5_clk_lookup[i].index) {
1222 return CMD_RET_USAGE;
1223 ref = CONFIG_SYS_MX5_HCLK;
1227 if (argc > 3 && ref > 3) {
1228 printf("Invalid clock selector value: %lu\n", ref);
1229 return CMD_RET_FAILURE;
1233 printf("Setting %s clock to %lu MHz\n",
1234 mx5_clk_lookup[i].name, freq);
1235 if (mxc_set_clock(ref, freq, mx5_clk_lookup[i].index))
1237 freq = mxc_get_clock(mx5_clk_lookup[i].index);
1238 printf("%s clock set to %lu.%03lu MHz\n",
1239 mx5_clk_lookup[i].name,
1240 freq / 1000000, freq / 1000 % 1000);
1241 return CMD_RET_SUCCESS;
1244 if (i == ARRAY_SIZE(mx5_clk_lookup)) {
1245 printf("clock %s not found; supported clocks are:\n", argv[1]);
1246 for (i = 0; i < ARRAY_SIZE(mx5_clk_lookup); i++) {
1247 printf("\t%s\n", mx5_clk_lookup[i].name);
1250 printf("Failed to set clock %s to %s MHz\n",
1253 return CMD_RET_FAILURE;
1256 /***************************************************/
1259 clocks, 4, 0, do_clocks,
1260 "display/set clocks",
1261 " - display clock settings\n"
1262 "clocks <clkname> <freq> - set clock <clkname> to <freq> MHz"