arch/arm/cpu/armv7/mx6/clock.c

   1 /*
   2  * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <asm/io.h>
   9 #include <asm/errno.h>
  10 #include <asm/arch/imx-regs.h>
  11 #include <asm/arch/crm_regs.h>
  12 #include <asm/arch/clock.h>
  13 #include <asm/arch/sys_proto.h>
  14
  15 enum pll_clocks {
  16         PLL_SYS,        /* System PLL */
  17         PLL_BUS,        /* System Bus PLL*/
  18         PLL_USBOTG,     /* OTG USB PLL */
  19         PLL_ENET,       /* ENET PLL */
  20 };
  21
  22 struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  23
  24 #ifdef CONFIG_MXC_OCOTP
  25 void enable_ocotp_clk(unsigned char enable)
  26 {
  27         u32 reg;
  28
  29         reg = __raw_readl(&imx_ccm->CCGR2);
  30         if (enable)
  31                 reg |= MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
  32         else
  33                 reg &= ~MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
  34         __raw_writel(reg, &imx_ccm->CCGR2);
  35 }
  36 #endif
  37
  38 void enable_usboh3_clk(unsigned char enable)
  39 {
  40         u32 reg;
  41
  42         reg = __raw_readl(&imx_ccm->CCGR6);
  43         if (enable)
  44                 reg |= MXC_CCM_CCGR6_USBOH3_MASK;
  45         else
  46                 reg &= ~(MXC_CCM_CCGR6_USBOH3_MASK);
  47         __raw_writel(reg, &imx_ccm->CCGR6);
  48
  49 }
  50
  51 #ifdef CONFIG_I2C_MXC
  52 /* i2c_num can be from 0 - 2 */
  53 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
  54 {
  55         u32 reg;
  56         u32 mask;
  57
  58         if (i2c_num > 2)
  59                 return -EINVAL;
  60
  61         mask = MXC_CCM_CCGR_CG_MASK
  62                 << (MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET + (i2c_num << 1));
  63         reg = __raw_readl(&imx_ccm->CCGR2);
  64         if (enable)
  65                 reg |= mask;
  66         else
  67                 reg &= ~mask;
  68         __raw_writel(reg, &imx_ccm->CCGR2);
  69         return 0;
  70 }
  71 #endif
  72
  73 static u32 decode_pll(enum pll_clocks pll, u32 infreq)
  74 {
  75         u32 div;
  76
  77         switch (pll) {
  78         case PLL_SYS:
  79                 div = __raw_readl(&imx_ccm->analog_pll_sys);
  80                 div &= BM_ANADIG_PLL_SYS_DIV_SELECT;
  81
  82                 return infreq * (div >> 1);
  83         case PLL_BUS:
  84                 div = __raw_readl(&imx_ccm->analog_pll_528);
  85                 div &= BM_ANADIG_PLL_528_DIV_SELECT;
  86
  87                 return infreq * (20 + (div << 1));
  88         case PLL_USBOTG:
  89                 div = __raw_readl(&imx_ccm->analog_usb1_pll_480_ctrl);
  90                 div &= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT;
  91
  92                 return infreq * (20 + (div << 1));
  93         case PLL_ENET:
  94                 div = __raw_readl(&imx_ccm->analog_pll_enet);
  95                 div &= BM_ANADIG_PLL_ENET_DIV_SELECT;
  96
  97                 return (div == 3 ? 125000000 : 25000000 * (div << 1));
  98         default:
  99                 return 0;
 100         }
 101         /* NOTREACHED */
 102 }
 103
 104 static u32 get_mcu_main_clk(void)
 105 {
 106         u32 reg, freq;
 107
 108         reg = __raw_readl(&imx_ccm->cacrr);
 109         reg &= MXC_CCM_CACRR_ARM_PODF_MASK;
 110         reg >>= MXC_CCM_CACRR_ARM_PODF_OFFSET;
 111         freq = decode_pll(PLL_SYS, MXC_HCLK);
 112
 113         return freq / (reg + 1);
 114 }
 115
 116 u32 get_periph_clk(void)
 117 {
 118         u32 reg, freq = 0;
 119
 120         reg = __raw_readl(&imx_ccm->cbcdr);
 121         if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
 122                 reg = __raw_readl(&imx_ccm->cbcmr);
 123                 reg &= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK;
 124                 reg >>= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET;
 125
 126                 switch (reg) {
 127                 case 0:
 128                         freq = decode_pll(PLL_USBOTG, MXC_HCLK);
 129                         break;
 130                 case 1:
 131                 case 2:
 132                         freq = MXC_HCLK;
 133                         break;
 134                 default:
 135                         break;
 136                 }
 137         } else {
 138                 reg = __raw_readl(&imx_ccm->cbcmr);
 139                 reg &= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK;
 140                 reg >>= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET;
 141
 142                 switch (reg) {
 143                 case 0:
 144                         freq = decode_pll(PLL_BUS, MXC_HCLK);
 145                         break;
 146                 case 1:
 147                         freq = PLL2_PFD2_FREQ;
 148                         break;
 149                 case 2:
 150                         freq = PLL2_PFD0_FREQ;
 151                         break;
 152                 case 3:
 153                         freq = PLL2_PFD2_DIV_FREQ;
 154                         break;
 155                 default:
 156                         break;
 157                 }
 158         }
 159
 160         return freq;
 161 }
 162
 163 static u32 get_ipg_clk(void)
 164 {
 165         u32 reg, ipg_podf;
 166
 167         reg = __raw_readl(&imx_ccm->cbcdr);
 168         reg &= MXC_CCM_CBCDR_IPG_PODF_MASK;
 169         ipg_podf = reg >> MXC_CCM_CBCDR_IPG_PODF_OFFSET;
 170
 171         return get_ahb_clk() / (ipg_podf + 1);
 172 }
 173
 174 static u32 get_ipg_per_clk(void)
 175 {
 176         u32 reg, perclk_podf;
 177
 178         reg = __raw_readl(&imx_ccm->cscmr1);
 179         perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
 180
 181         return get_ipg_clk() / (perclk_podf + 1);
 182 }
 183
 184 static u32 get_uart_clk(void)
 185 {
 186         u32 reg, uart_podf;
 187         u32 freq = PLL3_80M;
 188         reg = __raw_readl(&imx_ccm->cscdr1);
 189 #ifdef CONFIG_MX6SL
 190         if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
 191                 freq = MXC_HCLK;
 192 #endif
 193         reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
 194         uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
 195
 196         return freq / (uart_podf + 1);
 197 }
 198
 199 static u32 get_cspi_clk(void)
 200 {
 201         u32 reg, cspi_podf;
 202
 203         reg = __raw_readl(&imx_ccm->cscdr2);
 204         reg &= MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK;
 205         cspi_podf = reg >> MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
 206
 207         return  PLL3_60M / (cspi_podf + 1);
 208 }
 209
 210 static u32 get_axi_clk(void)
 211 {
 212         u32 root_freq, axi_podf;
 213         u32 cbcdr =  __raw_readl(&imx_ccm->cbcdr);
 214
 215         axi_podf = cbcdr & MXC_CCM_CBCDR_AXI_PODF_MASK;
 216         axi_podf >>= MXC_CCM_CBCDR_AXI_PODF_OFFSET;
 217
 218         if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) {
 219                 if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL)
 220                         root_freq = PLL2_PFD2_FREQ;
 221                 else
 222                         root_freq = PLL3_PFD1_FREQ;
 223         } else
 224                 root_freq = get_periph_clk();
 225
 226         return  root_freq / (axi_podf + 1);
 227 }
 228
 229 static u32 get_emi_slow_clk(void)
 230 {
 231         u32 emi_clk_sel, emi_slow_pof, cscmr1, root_freq = 0;
 232
 233         cscmr1 =  __raw_readl(&imx_ccm->cscmr1);
 234         emi_clk_sel = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK;
 235         emi_clk_sel >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET;
 236         emi_slow_pof = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK;
 237         emi_slow_pof >>= MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET;
 238
 239         switch (emi_clk_sel) {
 240         case 0:
 241                 root_freq = get_axi_clk();
 242                 break;
 243         case 1:
 244                 root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
 245                 break;
 246         case 2:
 247                 root_freq = PLL2_PFD2_FREQ;
 248                 break;
 249         case 3:
 250                 root_freq = PLL2_PFD0_FREQ;
 251                 break;
 252         }
 253
 254         return root_freq / (emi_slow_pof + 1);
 255 }
 256
 257 #ifdef CONFIG_MX6SL
 258 static u32 get_mmdc_ch0_clk(void)
 259 {
 260         u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
 261         u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
 262         u32 freq, podf;
 263
 264         podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) \
 265                         >> MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
 266
 267         switch ((cbcmr & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) >>
 268                 MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET) {
 269         case 0:
 270                 freq = decode_pll(PLL_BUS, MXC_HCLK);
 271                 break;
 272         case 1:
 273                 freq = PLL2_PFD2_FREQ;
 274                 break;
 275         case 2:
 276                 freq = PLL2_PFD0_FREQ;
 277                 break;
 278         case 3:
 279                 freq = PLL2_PFD2_DIV_FREQ;
 280         }
 281
 282         return freq / (podf + 1);
 283
 284 }
 285 #else
 286 static u32 get_mmdc_ch0_clk(void)
 287 {
 288         u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
 289         u32 mmdc_ch0_podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
 290                                 MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
 291
 292         return get_periph_clk() / (mmdc_ch0_podf + 1);
 293 }
 294 #endif
 295
 296 static u32 get_usdhc_clk(u32 port)
 297 {
 298         u32 root_freq = 0, usdhc_podf = 0, clk_sel = 0;
 299         u32 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
 300         u32 cscdr1 = __raw_readl(&imx_ccm->cscdr1);
 301
 302         switch (port) {
 303         case 0:
 304                 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >>
 305                                         MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET;
 306                 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC1_CLK_SEL;
 307
 308                 break;
 309         case 1:
 310                 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC2_PODF_MASK) >>
 311                                         MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET;
 312                 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC2_CLK_SEL;
 313
 314                 break;
 315         case 2:
 316                 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC3_PODF_MASK) >>
 317                                         MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET;
 318                 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC3_CLK_SEL;
 319
 320                 break;
 321         case 3:
 322                 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC4_PODF_MASK) >>
 323                                         MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET;
 324                 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC4_CLK_SEL;
 325
 326                 break;
 327         default:
 328                 break;
 329         }
 330
 331         if (clk_sel)
 332                 root_freq = PLL2_PFD0_FREQ;
 333         else
 334                 root_freq = PLL2_PFD2_FREQ;
 335
 336         return root_freq / (usdhc_podf + 1);
 337 }
 338
 339 u32 imx_get_uartclk(void)
 340 {
 341         return get_uart_clk();
 342 }
 343
 344 u32 imx_get_fecclk(void)
 345 {
 346         return decode_pll(PLL_ENET, MXC_HCLK);
 347 }
 348
 349 int enable_sata_clock(void)
 350 {
 351         u32 reg = 0;
 352         s32 timeout = 100000;
 353         struct mxc_ccm_reg *const imx_ccm
 354                 = (struct mxc_ccm_reg *) CCM_BASE_ADDR;
 355
 356         /* Enable sata clock */
 357         reg = readl(&imx_ccm->CCGR5); /* CCGR5 */
 358         reg |= MXC_CCM_CCGR5_SATA_MASK;
 359         writel(reg, &imx_ccm->CCGR5);
 360
 361         /* Enable PLLs */
 362         reg = readl(&imx_ccm->analog_pll_enet);
 363         reg &= ~BM_ANADIG_PLL_SYS_POWERDOWN;
 364         writel(reg, &imx_ccm->analog_pll_enet);
 365         reg |= BM_ANADIG_PLL_SYS_ENABLE;
 366         while (timeout--) {
 367                 if (readl(&imx_ccm->analog_pll_enet) & BM_ANADIG_PLL_SYS_LOCK)
 368                         break;
 369         }
 370         if (timeout <= 0)
 371                 return -EIO;
 372         reg &= ~BM_ANADIG_PLL_SYS_BYPASS;
 373         writel(reg, &imx_ccm->analog_pll_enet);
 374         reg |= BM_ANADIG_PLL_ENET_ENABLE_SATA;
 375         writel(reg, &imx_ccm->analog_pll_enet);
 376
 377         return 0 ;
 378 }
 379
 380 unsigned int mxc_get_clock(enum mxc_clock clk)
 381 {
 382         switch (clk) {
 383         case MXC_ARM_CLK:
 384                 return get_mcu_main_clk();
 385         case MXC_PER_CLK:
 386                 return get_periph_clk();
 387         case MXC_AHB_CLK:
 388                 return get_ahb_clk();
 389         case MXC_IPG_CLK:
 390                 return get_ipg_clk();
 391         case MXC_IPG_PERCLK:
 392         case MXC_I2C_CLK:
 393                 return get_ipg_per_clk();
 394         case MXC_UART_CLK:
 395                 return get_uart_clk();
 396         case MXC_CSPI_CLK:
 397                 return get_cspi_clk();
 398         case MXC_AXI_CLK:
 399                 return get_axi_clk();
 400         case MXC_EMI_SLOW_CLK:
 401                 return get_emi_slow_clk();
 402         case MXC_DDR_CLK:
 403                 return get_mmdc_ch0_clk();
 404         case MXC_ESDHC_CLK:
 405                 return get_usdhc_clk(0);
 406         case MXC_ESDHC2_CLK:
 407                 return get_usdhc_clk(1);
 408         case MXC_ESDHC3_CLK:
 409                 return get_usdhc_clk(2);
 410         case MXC_ESDHC4_CLK:
 411                 return get_usdhc_clk(3);
 412         case MXC_SATA_CLK:
 413                 return get_ahb_clk();
 414         default:
 415                 break;
 416         }
 417
 418         return -1;
 419 }
 420
 421 /*
 422  * Dump some core clockes.
 423  */
 424 int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 425 {
 426         u32 freq;
 427         freq = decode_pll(PLL_SYS, MXC_HCLK);
 428         printf("PLL_SYS    %8d MHz\n", freq / 1000000);
 429         freq = decode_pll(PLL_BUS, MXC_HCLK);
 430         printf("PLL_BUS    %8d MHz\n", freq / 1000000);
 431         freq = decode_pll(PLL_USBOTG, MXC_HCLK);
 432         printf("PLL_OTG    %8d MHz\n", freq / 1000000);
 433         freq = decode_pll(PLL_ENET, MXC_HCLK);
 434         printf("PLL_NET    %8d MHz\n", freq / 1000000);
 435
 436         printf("\n");
 437         printf("IPG        %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
 438         printf("UART       %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000);
 439 #ifdef CONFIG_MXC_SPI
 440         printf("CSPI       %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000);
 441 #endif
 442         printf("AHB        %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
 443         printf("AXI        %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000);
 444         printf("DDR        %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
 445         printf("USDHC1     %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000);
 446         printf("USDHC2     %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000);
 447         printf("USDHC3     %8d kHz\n", mxc_get_clock(MXC_ESDHC3_CLK) / 1000);
 448         printf("USDHC4     %8d kHz\n", mxc_get_clock(MXC_ESDHC4_CLK) / 1000);
 449         printf("EMI SLOW   %8d kHz\n", mxc_get_clock(MXC_EMI_SLOW_CLK) / 1000);
 450         printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK) / 1000);
 451
 452         return 0;
 453 }
 454
 455 /***************************************************/
 456
 457 U_BOOT_CMD(
 458         clocks, CONFIG_SYS_MAXARGS, 1, do_mx6_showclocks,
 459         "display clocks",
 460         ""
 461 );