2 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/errno.h>
11 #include <asm/arch/imx-regs.h>
12 #include <asm/arch/crm_regs.h>
13 #include <asm/arch/clock.h>
14 #include <asm/arch/sys_proto.h>
17 PLL_ARM, /* PLL1: ARM PLL */
18 PLL_528, /* PLL2: System Bus PLL*/
19 PLL_USBOTG, /* PLL3: OTG USB PLL */
20 PLL_AUDIO, /* PLL4: Audio PLL */
21 PLL_VIDEO, /* PLL5: Video PLL */
22 PLL_ENET, /* PLL6: ENET PLL */
23 PLL_USB2, /* PLL7: USB2 PLL */
24 PLL_MLB, /* PLL8: MLB PLL */
27 struct mxc_ccm_reg *const imx_ccm = (void *)CCM_BASE_ADDR;
28 struct anatop_regs *const anatop = (void *)ANATOP_BASE_ADDR;
30 int clk_enable(struct clk *clk)
36 if (clk->usecount == 0) {
37 debug("%s: Enabling %s clock\n", __func__, clk->name);
38 ret = clk->enable(clk);
43 assert(clk->usecount > 0);
47 void clk_disable(struct clk *clk)
52 assert(clk->usecount > 0);
53 if (!(--clk->usecount)) {
55 debug("%s: Disabling %s clock\n", __func__, clk->name);
61 int clk_get_usecount(struct clk *clk)
69 u32 clk_get_rate(struct clk *clk)
77 struct clk *clk_get_parent(struct clk *clk)
85 int clk_set_rate(struct clk *clk, unsigned long rate)
87 if (clk && clk->set_rate)
88 clk->set_rate(clk, rate);
92 long clk_round_rate(struct clk *clk, unsigned long rate)
94 if (clk == NULL || !clk->round_rate)
97 return clk->round_rate(clk, rate);
100 int clk_set_parent(struct clk *clk, struct clk *parent)
102 debug("Setting parent of clk %p to %p (%p)\n", clk, parent,
103 clk ? clk->parent : NULL);
105 if (!clk || clk == parent)
108 if (clk->set_parent) {
111 ret = clk->set_parent(clk, parent);
115 clk->parent = parent;
119 #ifdef CONFIG_MXC_OCOTP
120 void enable_ocotp_clk(unsigned char enable)
124 reg = __raw_readl(&imx_ccm->CCGR2);
126 reg |= MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
128 reg &= ~MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
129 __raw_writel(reg, &imx_ccm->CCGR2);
133 #ifdef CONFIG_NAND_MXS
134 void setup_gpmi_io_clk(u32 cfg)
136 /* Disable clocks per ERR007177 from MX6 errata */
137 clrbits_le32(&imx_ccm->CCGR4,
138 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
139 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
140 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
141 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
142 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
144 clrbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
146 clrsetbits_le32(&imx_ccm->cs2cdr,
147 MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
148 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
149 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
152 setbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
153 setbits_le32(&imx_ccm->CCGR4,
154 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
155 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
156 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
157 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
158 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
162 void enable_usboh3_clk(unsigned char enable)
166 reg = __raw_readl(&imx_ccm->CCGR6);
168 reg |= MXC_CCM_CCGR6_USBOH3_MASK;
170 reg &= ~(MXC_CCM_CCGR6_USBOH3_MASK);
171 __raw_writel(reg, &imx_ccm->CCGR6);
175 #if defined(CONFIG_FEC_MXC) && !defined(CONFIG_SOC_MX6SX)
176 void enable_enet_clk(unsigned char enable)
178 u32 mask = MXC_CCM_CCGR1_ENET_CLK_ENABLE_MASK;
181 setbits_le32(&imx_ccm->CCGR1, mask);
183 clrbits_le32(&imx_ccm->CCGR1, mask);
187 #ifdef CONFIG_MXC_UART
188 void enable_uart_clk(unsigned char enable)
190 u32 mask = MXC_CCM_CCGR5_UART_MASK | MXC_CCM_CCGR5_UART_SERIAL_MASK;
193 setbits_le32(&imx_ccm->CCGR5, mask);
195 clrbits_le32(&imx_ccm->CCGR5, mask);
200 /* spi_num can be from 0 - 4 */
201 int enable_cspi_clock(unsigned char enable, unsigned spi_num)
208 mask = MXC_CCM_CCGR_CG_MASK << (spi_num * 2);
210 setbits_le32(&imx_ccm->CCGR1, mask);
212 clrbits_le32(&imx_ccm->CCGR1, mask);
219 int enable_usdhc_clk(unsigned char enable, unsigned bus_num)
226 mask = MXC_CCM_CCGR_CG_MASK << (bus_num * 2 + 2);
228 setbits_le32(&imx_ccm->CCGR6, mask);
230 clrbits_le32(&imx_ccm->CCGR6, mask);
236 #ifdef CONFIG_SYS_I2C_MXC
237 /* i2c_num can be from 0 - 3 */
238 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
246 mask = MXC_CCM_CCGR_CG_MASK
247 << (MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET
249 reg = __raw_readl(&imx_ccm->CCGR2);
254 __raw_writel(reg, &imx_ccm->CCGR2);
256 mask = MXC_CCM_CCGR_CG_MASK
257 << (MXC_CCM_CCGR1_I2C4_SERIAL_OFFSET);
258 reg = __raw_readl(&imx_ccm->CCGR1);
263 __raw_writel(reg, &imx_ccm->CCGR1);
269 /* spi_num can be from 0 - SPI_MAX_NUM */
270 int enable_spi_clk(unsigned char enable, unsigned spi_num)
275 if (spi_num > SPI_MAX_NUM)
278 mask = MXC_CCM_CCGR_CG_MASK << (spi_num << 1);
279 reg = __raw_readl(&imx_ccm->CCGR1);
284 __raw_writel(reg, &imx_ccm->CCGR1);
287 static u32 decode_pll(enum pll_clocks pll, u32 infreq)
293 div = __raw_readl(&anatop->pll_arm);
294 if (div & BM_ANADIG_PLL_ARM_BYPASS)
295 /* Assume the bypass clock is always derived from OSC */
297 div &= BM_ANADIG_PLL_ARM_DIV_SELECT;
299 return infreq * div / 2;
301 div = __raw_readl(&anatop->pll_528);
302 if (div & BM_ANADIG_PLL_528_BYPASS)
304 div &= BM_ANADIG_PLL_528_DIV_SELECT;
306 return infreq * (20 + div * 2);
308 div = __raw_readl(&anatop->usb1_pll_480_ctrl);
309 if (div & BM_ANADIG_USB_PLL_480_CTRL_BYPASS)
311 div &= BM_ANADIG_USB_PLL_480_CTRL_DIV_SELECT;
313 return infreq * (20 + div * 2);
315 div = __raw_readl(&anatop->pll_audio);
316 if (div & BM_ANADIG_PLL_AUDIO_BYPASS)
318 div &= BM_ANADIG_PLL_AUDIO_DIV_SELECT;
322 div = __raw_readl(&anatop->pll_video);
323 if (div & BM_ANADIG_PLL_VIDEO_BYPASS)
325 div &= BM_ANADIG_PLL_VIDEO_DIV_SELECT;
329 div = __raw_readl(&anatop->pll_enet);
330 if (div & BM_ANADIG_PLL_ENET_BYPASS)
332 div &= BM_ANADIG_PLL_ENET_DIV_SELECT;
334 return 25000000 * (div + (div >> 1) + 1);
336 div = __raw_readl(&anatop->usb2_pll_480_ctrl);
337 if (div & BM_ANADIG_USB_PLL_480_CTRL_BYPASS)
339 div &= BM_ANADIG_USB_PLL_480_CTRL_DIV_SELECT;
341 return infreq * (20 + div * 2);
343 div = __raw_readl(&anatop->pll_mlb);
344 if (div & BM_ANADIG_PLL_MLB_BYPASS)
346 /* unknown external clock provided on MLB_CLK pin */
351 static u32 mxc_get_pll_pfd(enum pll_clocks pll, int pfd_num)
355 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
360 /* No PFD3 on PLL2 */
363 div = __raw_readl(&anatop->pfd_528);
364 freq = (u64)decode_pll(PLL_528, MXC_HCLK);
367 div = __raw_readl(&anatop->pfd_480);
368 freq = (u64)decode_pll(PLL_USBOTG, MXC_HCLK);
371 /* No PFD on other PLL */
375 return lldiv(freq * 18, (div & ANATOP_PFD_FRAC_MASK(pfd_num)) >>
376 ANATOP_PFD_FRAC_SHIFT(pfd_num));
379 static u32 get_mcu_main_clk(void)
383 reg = __raw_readl(&imx_ccm->cacrr);
384 reg &= MXC_CCM_CACRR_ARM_PODF_MASK;
385 reg >>= MXC_CCM_CACRR_ARM_PODF_OFFSET;
386 freq = decode_pll(PLL_ARM, MXC_HCLK);
388 return freq / (reg + 1);
391 u32 get_periph_clk(void)
395 reg = __raw_readl(&imx_ccm->cbcdr);
396 if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
397 reg = __raw_readl(&imx_ccm->cbcmr);
398 reg &= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK;
399 reg >>= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET;
403 freq = decode_pll(PLL_USBOTG, MXC_HCLK);
411 reg = __raw_readl(&imx_ccm->cbcmr);
412 reg &= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK;
413 reg >>= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET;
417 freq = decode_pll(PLL_528, MXC_HCLK);
420 freq = mxc_get_pll_pfd(PLL_528, 2);
423 freq = mxc_get_pll_pfd(PLL_528, 0);
426 /* static / 2 divider */
427 freq = mxc_get_pll_pfd(PLL_528, 2) / 2;
435 static u32 get_ipg_clk(void)
439 reg = __raw_readl(&imx_ccm->cbcdr);
440 reg &= MXC_CCM_CBCDR_IPG_PODF_MASK;
441 ipg_podf = reg >> MXC_CCM_CBCDR_IPG_PODF_OFFSET;
443 return get_ahb_clk() / (ipg_podf + 1);
446 static u32 get_ipg_per_clk(void)
448 u32 reg, perclk_podf;
450 reg = __raw_readl(&imx_ccm->cscmr1);
451 #if (defined(CONFIG_SOC_MX6SL) || defined(CONFIG_SOC_MX6SX))
452 if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
453 return MXC_HCLK; /* OSC 24Mhz */
455 perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
457 return get_ipg_clk() / (perclk_podf + 1);
460 static u32 get_uart_clk(void)
463 u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */
464 reg = __raw_readl(&imx_ccm->cscdr1);
465 #if (defined(CONFIG_SOC_MX6SL) || defined(CONFIG_SOC_MX6SX))
466 if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
469 reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
470 uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
472 return freq / (uart_podf + 1);
475 static u32 get_cspi_clk(void)
479 reg = __raw_readl(&imx_ccm->cscdr2);
480 reg &= MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK;
481 cspi_podf = reg >> MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
483 return decode_pll(PLL_USBOTG, MXC_HCLK) / (8 * (cspi_podf + 1));
486 static u32 get_axi_clk(void)
488 u32 root_freq, axi_podf;
489 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
491 axi_podf = cbcdr & MXC_CCM_CBCDR_AXI_PODF_MASK;
492 axi_podf >>= MXC_CCM_CBCDR_AXI_PODF_OFFSET;
494 if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) {
495 if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL)
496 root_freq = mxc_get_pll_pfd(PLL_528, 2);
498 root_freq = mxc_get_pll_pfd(PLL_USBOTG, 1);
500 root_freq = get_periph_clk();
502 return root_freq / (axi_podf + 1);
505 static u32 get_emi_slow_clk(void)
507 u32 emi_clk_sel, emi_slow_podf, cscmr1, root_freq = 0;
509 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
510 emi_clk_sel = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK;
511 emi_clk_sel >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET;
512 emi_slow_podf = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK;
513 emi_slow_podf >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET;
515 switch (emi_clk_sel) {
517 root_freq = get_axi_clk();
520 root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
523 root_freq = mxc_get_pll_pfd(PLL_528, 2);
526 root_freq = mxc_get_pll_pfd(PLL_528, 0);
530 return root_freq / (emi_slow_podf + 1);
533 static u32 get_nfc_clk(void)
535 u32 cs2cdr = __raw_readl(&imx_ccm->cs2cdr);
536 u32 podf = (cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK) >> MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET;
537 u32 pred = (cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK) >> MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET;
538 int nfc_clk_sel = (cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK) >>
539 MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET;
542 switch (nfc_clk_sel) {
544 root_freq = mxc_get_pll_pfd(PLL_528, 0);
547 root_freq = decode_pll(PLL_528, MXC_HCLK);
550 root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
553 root_freq = mxc_get_pll_pfd(PLL_528, 2);
557 return root_freq / (pred + 1) / (podf + 1);
560 #define CS2CDR_ENFC_MASK (MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK | \
561 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK | \
562 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK)
564 static int set_nfc_clk(u32 ref, u32 freq_khz)
566 u32 cs2cdr = __raw_readl(&imx_ccm->cs2cdr);
573 u32 freq = freq_khz * 1000;
575 for (nfc_clk_sel = 0; nfc_clk_sel < 4; nfc_clk_sel++) {
579 if (ref < 4 && ref != nfc_clk_sel)
582 switch (nfc_clk_sel) {
584 root_freq = mxc_get_pll_pfd(PLL_528, 0);
587 root_freq = decode_pll(PLL_528, MXC_HCLK);
590 root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
593 root_freq = mxc_get_pll_pfd(PLL_528, 2);
596 if (root_freq < freq)
599 podf = min(DIV_ROUND_UP(root_freq, freq), 1U << 6);
600 pred = min(DIV_ROUND_UP(root_freq / podf, freq), 8U);
601 act_freq = root_freq / pred / podf;
602 err = (freq - act_freq) * 100 / freq;
603 debug("root=%d[%u] freq=%u pred=%u podf=%u act=%u err=%d\n",
604 nfc_clk_sel, root_freq, freq, pred, podf, act_freq, err);
608 nfc_val = (podf - 1) << MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET;
609 nfc_val |= (pred - 1) << MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET;
610 nfc_val |= nfc_clk_sel << MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET;
617 if (nfc_val == ~0 || min_err > 10)
620 if ((cs2cdr & CS2CDR_ENFC_MASK) != nfc_val) {
621 debug("changing cs2cdr from %08x to %08x\n", cs2cdr,
622 (cs2cdr & ~CS2CDR_ENFC_MASK) | nfc_val);
623 __raw_writel((cs2cdr & ~CS2CDR_ENFC_MASK) | nfc_val,
626 debug("Leaving cs2cdr unchanged [%08x]\n", cs2cdr);
631 #if (defined(CONFIG_SOC_MX6SL) || defined(CONFIG_SOC_MX6SX))
632 static u32 get_mmdc_ch0_clk(void)
634 u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
635 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
638 podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) \
639 >> MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
641 switch ((cbcmr & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) >>
642 MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET) {
644 freq = decode_pll(PLL_528, MXC_HCLK);
647 freq = mxc_get_pll_pfd(PLL_528, 2);
650 freq = mxc_get_pll_pfd(PLL_528, 0);
653 /* static / 2 divider */
654 freq = mxc_get_pll_pfd(PLL_528, 2) / 2;
657 return freq / (podf + 1);
661 static u32 get_mmdc_ch0_clk(void)
663 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
664 u32 mmdc_ch0_podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
665 MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
667 return get_periph_clk() / (mmdc_ch0_podf + 1);
671 #ifdef CONFIG_SOC_MX6SX
672 /* qspi_num can be from 0 - 1 */
673 void enable_qspi_clk(int qspi_num)
676 /* Enable QuadSPI clock */
679 /* disable the clock gate */
680 clrbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
682 /* set 50M : (50 = 396 / 2 / 4) */
683 reg = readl(&imx_ccm->cscmr1);
684 reg &= ~(MXC_CCM_CSCMR1_QSPI1_PODF_MASK |
685 MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK);
686 reg |= ((1 << MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET) |
687 (2 << MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET));
688 writel(reg, &imx_ccm->cscmr1);
690 /* enable the clock gate */
691 setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
695 * disable the clock gate
696 * QSPI2 and GPMI_BCH_INPUT_GPMI_IO share the same clock gate,
697 * disable both of them.
699 clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
700 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
702 /* set 50M : (50 = 396 / 2 / 4) */
703 reg = readl(&imx_ccm->cs2cdr);
704 reg &= ~(MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK |
705 MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK |
706 MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK);
707 reg |= (MXC_CCM_CS2CDR_QSPI2_CLK_PRED(0x1) |
708 MXC_CCM_CS2CDR_QSPI2_CLK_SEL(0x3));
709 writel(reg, &imx_ccm->cs2cdr);
711 /*enable the clock gate*/
712 setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
713 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
721 #ifdef CONFIG_FEC_MXC
722 int enable_fec_anatop_clock(enum enet_freq freq)
725 s32 timeout = 100000;
727 struct anatop_regs __iomem *anatop =
728 (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
730 if (freq < ENET_25MHZ || freq > ENET_125MHZ)
733 reg = readl(&anatop->pll_enet);
734 reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT;
737 if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) ||
738 (!(reg & BM_ANADIG_PLL_ENET_LOCK))) {
739 reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN;
740 writel(reg, &anatop->pll_enet);
742 if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK)
749 /* Enable FEC clock */
750 reg |= BM_ANADIG_PLL_ENET_ENABLE;
751 reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
752 writel(reg, &anatop->pll_enet);
754 #ifdef CONFIG_SOC_MX6SX
756 * Set enet ahb clock to 200MHz
757 * pll2_pfd2_396m-> ENET_PODF-> ENET_AHB
759 reg = readl(&imx_ccm->chsccdr);
760 reg &= ~(MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK
761 | MXC_CCM_CHSCCDR_ENET_PODF_MASK
762 | MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK);
764 reg |= (4 << MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET);
766 reg |= (1 << MXC_CCM_CHSCCDR_ENET_PODF_OFFSET);
767 reg |= (0 << MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET);
768 writel(reg, &imx_ccm->chsccdr);
770 /* Enable enet system clock */
771 reg = readl(&imx_ccm->CCGR3);
772 reg |= MXC_CCM_CCGR3_ENET_MASK;
773 writel(reg, &imx_ccm->CCGR3);
779 static u32 get_usdhc_clk(u32 port)
781 u32 root_freq = 0, usdhc_podf = 0, clk_sel = 0;
782 u32 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
783 u32 cscdr1 = __raw_readl(&imx_ccm->cscdr1);
787 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >>
788 MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET;
789 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC1_CLK_SEL;
793 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC2_PODF_MASK) >>
794 MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET;
795 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC2_CLK_SEL;
799 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC3_PODF_MASK) >>
800 MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET;
801 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC3_CLK_SEL;
805 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC4_PODF_MASK) >>
806 MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET;
807 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC4_CLK_SEL;
815 root_freq = mxc_get_pll_pfd(PLL_528, 0);
817 root_freq = mxc_get_pll_pfd(PLL_528, 2);
819 return root_freq / (usdhc_podf + 1);
822 u32 imx_get_uartclk(void)
824 return get_uart_clk();
827 u32 imx_get_fecclk(void)
829 return mxc_get_clock(MXC_IPG_CLK);
832 static int enable_enet_pll(uint32_t en)
835 s32 timeout = 100000;
838 reg = readl(&anatop->pll_enet);
839 reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN;
840 writel(reg, &anatop->pll_enet);
841 reg |= BM_ANADIG_PLL_ENET_ENABLE;
843 if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK)
848 reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
849 writel(reg, &anatop->pll_enet);
851 writel(reg, &anatop->pll_enet);
855 #ifndef CONFIG_SOC_MX6SX
856 static void ungate_sata_clock(void)
858 struct mxc_ccm_reg *const imx_ccm =
859 (struct mxc_ccm_reg *)CCM_BASE_ADDR;
861 /* Enable SATA clock. */
862 setbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
866 static void ungate_pcie_clock(void)
868 struct mxc_ccm_reg *const imx_ccm =
869 (struct mxc_ccm_reg *)CCM_BASE_ADDR;
871 /* Enable PCIe clock. */
872 setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_PCIE_MASK);
875 #ifndef CONFIG_SOC_MX6SX
876 int enable_sata_clock(void)
879 return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA);
882 void disable_sata_clock(void)
884 struct mxc_ccm_reg *const imx_ccm =
885 (struct mxc_ccm_reg *)CCM_BASE_ADDR;
887 clrbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
891 int enable_pcie_clock(void)
893 struct anatop_regs *anatop_regs =
894 (struct anatop_regs *)ANATOP_BASE_ADDR;
895 struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
901 * The register ANATOP_MISC1 is not documented in the Freescale
902 * MX6RM. The register that is mapped in the ANATOP space and
903 * marked as ANATOP_MISC1 is actually documented in the PMU section
904 * of the datasheet as PMU_MISC1.
906 * Switch LVDS clock source to SATA (0xb) on mx6q/dl or PCI (0xa) on
907 * mx6sx, disable clock INPUT and enable clock OUTPUT. This is important
908 * for PCI express link that is clocked from the i.MX6.
910 #define ANADIG_ANA_MISC1_LVDSCLK1_IBEN (1 << 12)
911 #define ANADIG_ANA_MISC1_LVDSCLK1_OBEN (1 << 10)
912 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK 0x0000001F
913 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF 0xa
914 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF 0xb
916 if (is_cpu_type(MXC_CPU_MX6SX))
917 lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF;
919 lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF;
921 clrsetbits_le32(&anatop_regs->ana_misc1,
922 ANADIG_ANA_MISC1_LVDSCLK1_IBEN |
923 ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK,
924 ANADIG_ANA_MISC1_LVDSCLK1_OBEN | lvds1_clk_sel);
926 /* PCIe reference clock sourced from AXI. */
927 clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL);
929 /* Party time! Ungate the clock to the PCIe. */
930 #ifndef CONFIG_SOC_MX6SX
935 return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA |
936 BM_ANADIG_PLL_ENET_ENABLE_PCIE);
939 #ifdef CONFIG_SECURE_BOOT
940 void hab_caam_clock_enable(unsigned char enable)
944 /* CG4 ~ CG6, CAAM clocks */
945 reg = __raw_readl(&imx_ccm->CCGR0);
947 reg |= (MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
948 MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
949 MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
951 reg &= ~(MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
952 MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
953 MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
954 __raw_writel(reg, &imx_ccm->CCGR0);
957 reg = __raw_readl(&imx_ccm->CCGR6);
959 reg |= MXC_CCM_CCGR6_EMI_SLOW_MASK;
961 reg &= ~MXC_CCM_CCGR6_EMI_SLOW_MASK;
962 __raw_writel(reg, &imx_ccm->CCGR6);
966 static void enable_pll3(void)
968 struct anatop_regs __iomem *anatop =
969 (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
971 /* make sure pll3 is enabled */
972 if ((readl(&anatop->usb1_pll_480_ctrl) &
973 BM_ANADIG_USB_PLL_480_CTRL_LOCK) == 0) {
974 /* enable pll's power */
975 writel(BM_ANADIG_USB_PLL_480_CTRL_POWER,
976 &anatop->usb1_pll_480_ctrl_set);
977 writel(0x80, &anatop->ana_misc2_clr);
978 /* wait for pll lock */
979 while ((readl(&anatop->usb1_pll_480_ctrl) &
980 BM_ANADIG_USB_PLL_480_CTRL_LOCK) == 0)
983 writel(BM_ANADIG_USB_PLL_480_CTRL_BYPASS,
984 &anatop->usb1_pll_480_ctrl_clr);
985 /* enable pll output */
986 writel(BM_ANADIG_USB_PLL_480_CTRL_ENABLE,
987 &anatop->usb1_pll_480_ctrl_set);
991 void enable_thermal_clk(void)
996 void ipu_clk_enable(void)
998 u32 reg = readl(&imx_ccm->CCGR3);
999 reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
1000 writel(reg, &imx_ccm->CCGR3);
1003 void ipu_clk_disable(void)
1005 u32 reg = readl(&imx_ccm->CCGR3);
1006 reg &= ~MXC_CCM_CCGR3_IPU1_IPU_MASK;
1007 writel(reg, &imx_ccm->CCGR3);
1010 void ipu_di_clk_enable(int di)
1014 setbits_le32(&imx_ccm->CCGR3,
1015 MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK);
1018 setbits_le32(&imx_ccm->CCGR3,
1019 MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK);
1022 printf("%s: Invalid DI index %d\n", __func__, di);
1026 void ipu_di_clk_disable(int di)
1030 clrbits_le32(&imx_ccm->CCGR3,
1031 MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK);
1034 clrbits_le32(&imx_ccm->CCGR3,
1035 MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK);
1038 printf("%s: Invalid DI index %d\n", __func__, di);
1042 void ldb_clk_enable(int ldb)
1046 setbits_le32(&imx_ccm->CCGR3,
1047 MXC_CCM_CCGR3_LDB_DI0_MASK);
1050 setbits_le32(&imx_ccm->CCGR3,
1051 MXC_CCM_CCGR3_LDB_DI1_MASK);
1054 printf("%s: Invalid LDB index %d\n", __func__, ldb);
1058 void ldb_clk_disable(int ldb)
1062 clrbits_le32(&imx_ccm->CCGR3,
1063 MXC_CCM_CCGR3_LDB_DI0_MASK);
1066 clrbits_le32(&imx_ccm->CCGR3,
1067 MXC_CCM_CCGR3_LDB_DI1_MASK);
1070 printf("%s: Invalid LDB index %d\n", __func__, ldb);
1074 void ocotp_clk_enable(void)
1076 u32 reg = readl(&imx_ccm->CCGR2);
1077 reg |= MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
1078 writel(reg, &imx_ccm->CCGR2);
1081 void ocotp_clk_disable(void)
1083 u32 reg = readl(&imx_ccm->CCGR2);
1084 reg &= ~MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
1085 writel(reg, &imx_ccm->CCGR2);
1088 unsigned int mxc_get_clock(enum mxc_clock clk)
1092 return get_mcu_main_clk();
1094 return get_periph_clk();
1096 return get_ahb_clk();
1098 return get_ipg_clk();
1099 case MXC_IPG_PERCLK:
1101 return get_ipg_per_clk();
1103 return get_uart_clk();
1105 return get_cspi_clk();
1107 return get_axi_clk();
1108 case MXC_EMI_SLOW_CLK:
1109 return get_emi_slow_clk();
1111 return get_mmdc_ch0_clk();
1113 return get_usdhc_clk(0);
1114 case MXC_ESDHC2_CLK:
1115 return get_usdhc_clk(1);
1116 case MXC_ESDHC3_CLK:
1117 return get_usdhc_clk(2);
1118 case MXC_ESDHC4_CLK:
1119 return get_usdhc_clk(3);
1121 return get_ahb_clk();
1123 return get_nfc_clk();
1125 printf("Unsupported MXC CLK: %d\n", clk);
1131 static inline int gcd(int m, int n)
1145 /* Config CPU clock */
1146 static int set_arm_clk(u32 ref, u32 freq_khz)
1154 if (freq_khz > ref / 1000 * 108 / 2 || freq_khz < ref / 1000 * 54 / 8 / 2) {
1155 printf("Frequency %u.%03uMHz is out of range: %u.%03u..%u.%03u\n",
1156 freq_khz / 1000, freq_khz % 1000,
1157 54 * ref / 1000000 / 8 / 2, 54 * ref / 1000 / 8 / 2 % 1000,
1158 108 * ref / 1000000 / 2, 108 * ref / 1000 / 2 % 1000);
1162 for (d = DIV_ROUND_UP(648000, freq_khz); d <= 8; d++) {
1163 int m = freq_khz * 2 * d / (ref / 1000);
1168 debug("%s@%d: d=%d m=%d\n", __func__, __LINE__,
1173 f = ref * m / d / 2;
1174 if (f > freq_khz * 1000) {
1175 debug("%s@%d: d=%d m=%d f=%u freq=%u\n", __func__, __LINE__,
1179 f = ref * m / d / 2;
1181 err = freq_khz * 1000 - f;
1182 debug("%s@%d: d=%d m=%d f=%u freq=%u err=%d\n", __func__, __LINE__,
1183 d, m, f, freq_khz, err);
1184 if (err < min_err) {
1194 debug("Setting M=%3u D=%2u for %u.%03uMHz (actual: %u.%03uMHz)\n",
1195 mul, div, freq_khz / 1000, freq_khz % 1000,
1196 ref * mul / 2 / div / 1000000, ref * mul / 2 / div / 1000 % 1000);
1198 reg = readl(&anatop->pll_arm);
1199 debug("anadig_pll_arm=%08x -> %08x\n",
1200 reg, (reg & ~0x7f) | mul);
1203 writel(reg, &anatop->pll_arm); /* bypass PLL */
1205 reg = (reg & ~0x7f) | mul;
1206 writel(reg, &anatop->pll_arm);
1208 writel(div - 1, &imx_ccm->cacrr);
1211 writel(reg, &anatop->pll_arm); /* disable PLL bypass */
1217 * This function assumes the expected core clock has to be changed by
1218 * modifying the PLL. This is NOT true always but for most of the times,
1219 * it is. So it assumes the PLL output freq is the same as the expected
1220 * core clock (presc=1) unless the core clock is less than PLL_FREQ_MIN.
1221 * In the latter case, it will try to increase the presc value until
1222 * (presc*core_clk) is greater than PLL_FREQ_MIN. It then makes call to
1223 * calc_pll_params() and obtains the values of PD, MFI,MFN, MFD based
1224 * on the targeted PLL and reference input clock to the PLL. Lastly,
1225 * it sets the register based on these values along with the dividers.
1226 * Note 1) There is no value checking for the passed-in divider values
1227 * so the caller has to make sure those values are sensible.
1228 * 2) Also adjust the NFC divider such that the NFC clock doesn't
1229 * exceed NFC_CLK_MAX.
1230 * 3) IPU HSP clock is independent of AHB clock. Even it can go up to
1231 * 177MHz for higher voltage, this function fixes the max to 133MHz.
1232 * 4) This function should not have allowed diag_printf() calls since
1233 * the serial driver has been stoped. But leave then here to allow
1234 * easy debugging by NOT calling the cyg_hal_plf_serial_stop().
1236 int mxc_set_clock(u32 ref, u32 freq, enum mxc_clock clk)
1244 ret = set_arm_clk(ref, freq);
1248 ret = set_nfc_clk(ref, freq);
1252 printf("Warning: Unsupported or invalid clock type: %d\n",
1261 * Dump some core clocks.
1263 #define print_pll(pll) { \
1264 u32 __pll = decode_pll(pll, MXC_HCLK); \
1265 printf("%-12s %4d.%03d MHz\n", #pll, \
1266 __pll / 1000000, __pll / 1000 % 1000); \
1269 #define MXC_IPG_PER_CLK MXC_IPG_PERCLK
1271 #define print_clk(clk) { \
1272 u32 __clk = mxc_get_clock(MXC_##clk##_CLK); \
1273 printf("%-12s %4d.%03d MHz\n", #clk, \
1274 __clk / 1000000, __clk / 1000 % 1000); \
1277 #define print_pfd(pll, pfd) { \
1278 u32 __pfd = readl(&anatop->pfd_##pll); \
1279 if (__pfd & (0x80 << 8 * pfd)) { \
1280 printf("PFD_%s[%d] OFF\n", #pll, pfd); \
1282 __pfd = (__pfd >> 8 * pfd) & 0x3f; \
1283 printf("PFD_%s[%d] %4d.%03d MHz\n", #pll, pfd, \
1285 pll * 18 * 1000 / __pfd % 1000); \
1289 static void do_mx6_showclocks(void)
1293 print_pll(PLL_USBOTG);
1294 print_pll(PLL_AUDIO);
1295 print_pll(PLL_VIDEO);
1296 print_pll(PLL_ENET);
1297 print_pll(PLL_USB2);
1319 print_clk(EMI_SLOW);
1325 static struct clk_lookup {
1328 } mx6_clk_lookup[] = {
1329 { "arm", MXC_ARM_CLK, },
1330 { "nfc", MXC_NFC_CLK, },
1333 int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
1337 unsigned long ref = ~0UL;
1340 do_mx6_showclocks();
1341 return CMD_RET_SUCCESS;
1342 } else if (argc == 2 || argc > 4) {
1343 return CMD_RET_USAGE;
1346 freq = simple_strtoul(argv[2], NULL, 0);
1348 printf("Invalid clock frequency %lu\n", freq);
1349 return CMD_RET_FAILURE;
1352 ref = simple_strtoul(argv[3], NULL, 0);
1354 for (i = 0; i < ARRAY_SIZE(mx6_clk_lookup); i++) {
1355 if (strcasecmp(argv[1], mx6_clk_lookup[i].name) == 0) {
1356 switch (mx6_clk_lookup[i].index) {
1359 return CMD_RET_USAGE;
1364 if (argc > 3 && ref > 3) {
1365 printf("Invalid clock selector value: %lu\n", ref);
1366 return CMD_RET_FAILURE;
1370 printf("Setting %s clock to %lu MHz\n",
1371 mx6_clk_lookup[i].name, freq);
1372 if (mxc_set_clock(ref, freq, mx6_clk_lookup[i].index))
1374 freq = mxc_get_clock(mx6_clk_lookup[i].index);
1375 printf("%s clock set to %lu.%03lu MHz\n",
1376 mx6_clk_lookup[i].name,
1377 freq / 1000000, freq / 1000 % 1000);
1378 return CMD_RET_SUCCESS;
1381 if (i == ARRAY_SIZE(mx6_clk_lookup)) {
1382 printf("clock %s not found; supported clocks are:\n", argv[1]);
1383 for (i = 0; i < ARRAY_SIZE(mx6_clk_lookup); i++) {
1384 printf("\t%s\n", mx6_clk_lookup[i].name);
1387 printf("Failed to set clock %s to %s MHz\n",
1390 return CMD_RET_FAILURE;
1393 #ifndef CONFIG_SOC_MX6SX
1394 void enable_ipu_clock(void)
1396 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1398 reg = readl(&mxc_ccm->CCGR3);
1399 reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
1400 writel(reg, &mxc_ccm->CCGR3);
1403 /***************************************************/
1406 clocks, 4, 0, do_clocks,
1407 "display/set clocks",
1408 " - display clock settings\n"
1409 "clocks <clkname> <freq> - set clock <clkname> to <freq> MHz"