3 * Sascha Hauer, Pengutronix
5 * (C) Copyright 2009 Freescale Semiconductor, Inc.
7 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm/armv7.h>
16 #include <asm/bootm.h>
17 #include <asm/pl310.h>
18 #include <asm/errno.h>
20 #include <asm/arch/imx-regs.h>
21 #include <asm/arch/clock.h>
22 #include <asm/arch/regs-ocotp.h>
23 #include <asm/arch/sys_proto.h>
24 #include <asm/imx-common/boot_mode.h>
25 #include <asm/imx-common/dma.h>
27 #include <asm/arch/mxc_hdmi.h>
28 #include <asm/arch/crm_regs.h>
30 #include <imx_thermal.h>
32 DECLARE_GLOBAL_DATA_PTR;
34 #define __data __attribute__((section(".data")))
36 #ifdef CONFIG_MX6_TEMPERATURE_MIN
37 #define TEMPERATURE_MIN CONFIG_MX6_TEMPERATURE_MIN
39 #define TEMPERATURE_MIN (-40)
41 #ifdef CONFIG_MX6_TEMPERATURE_HOT
42 #define TEMPERATURE_HOT CONFIG_MX6_TEMPERATURE_HOT
44 #define TEMPERATURE_HOT 80
46 #ifdef CONFIG_MX6_TEMPERATURE_MAX
47 #define TEMPERATURE_MAX CONFIG_MX6_TEMPERATURE_MAX
49 #define TEMPERATURE_MAX 125
51 #define TEMP_AVG_COUNT 5
52 #define TEMP_WARN_THRESHOLD 5
68 #if defined(CONFIG_IMX6_THERMAL)
69 static const struct imx_thermal_plat imx6_thermal_plat = {
70 .regs = (void *)ANATOP_BASE_ADDR,
75 U_BOOT_DEVICE(imx6_thermal) = {
76 .name = "imx_thermal",
77 .platdata = &imx6_thermal_plat,
83 struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
84 return readl(&scu->config) & 3;
89 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
90 u32 reg = readl(&anatop->digprog_sololite);
91 u32 type = ((reg >> 16) & 0xff);
94 if (type != MXC_CPU_MX6SL) {
95 reg = readl(&anatop->digprog);
96 struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
97 cfg = readl(&scu->config) & 3;
98 type = ((reg >> 16) & 0xff);
99 if (type == MXC_CPU_MX6DL) {
101 type = MXC_CPU_MX6SOLO;
104 if (type == MXC_CPU_MX6Q) {
110 major = ((reg >> 8) & 0xff);
112 ((type == MXC_CPU_MX6Q) || (type == MXC_CPU_MX6D))) {
114 type = MXC_CPU_MX6QP;
116 type = MXC_CPU_MX6DP;
118 reg &= 0xff; /* mx6 silicon revision */
119 return (type << 12) | (reg + (0x10 * (major + 1)));
123 * OCOTP_CFG3[17:16] (see Fusemap Description Table offset 0x440)
124 * defines a 2-bit SPEED_GRADING
126 #define OCOTP_CFG3_SPEED_SHIFT 16
127 #define OCOTP_CFG3_SPEED_800MHZ 0
128 #define OCOTP_CFG3_SPEED_850MHZ 1
129 #define OCOTP_CFG3_SPEED_1GHZ 2
130 #define OCOTP_CFG3_SPEED_1P2GHZ 3
132 u32 get_cpu_speed_grade_hz(void)
136 if (fuse_read(0, 3, &val)) {
137 printf("Failed to read speed_grade fuse\n");
140 val >>= OCOTP_CFG3_SPEED_SHIFT;
144 /* Valid for IMX6DQ */
145 case OCOTP_CFG3_SPEED_1P2GHZ:
146 if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
148 /* Valid for IMX6SX/IMX6SDL/IMX6DQ */
149 case OCOTP_CFG3_SPEED_1GHZ:
151 /* Valid for IMX6DQ */
152 case OCOTP_CFG3_SPEED_850MHZ:
153 if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
155 /* Valid for IMX6SX/IMX6SDL/IMX6DQ/IMX6ULL */
156 case OCOTP_CFG3_SPEED_800MHZ:
163 * OCOTP_MEM0[7:6] (see Fusemap Description Table offset 0x480)
164 * defines a 2-bit Temperature Grade
166 * return temperature grade and min/max temperature in celcius
168 #define OCOTP_MEM0_TEMP_SHIFT 6
170 u32 get_cpu_temp_grade(int *minc, int *maxc)
174 if (fuse_read(1, 0, &val)) {
175 printf("Failed to read temp_grade fuse\n");
178 val >>= OCOTP_MEM0_TEMP_SHIFT;
182 if (val == TEMP_AUTOMOTIVE) {
185 } else if (val == TEMP_INDUSTRIAL) {
188 } else if (val == TEMP_EXTCOMMERCIAL) {
199 #ifdef CONFIG_REVISION_TAG
200 u32 __weak get_board_rev(void)
202 u32 cpurev = get_cpu_rev();
203 u32 type = ((cpurev >> 12) & 0xff);
204 if (type == MXC_CPU_MX6SOLO)
205 cpurev = (MXC_CPU_MX6DL) << 12 | (cpurev & 0xFFF);
207 if (type == MXC_CPU_MX6D)
208 cpurev = (MXC_CPU_MX6Q) << 12 | (cpurev & 0xFFF);
216 struct aipstz_regs *aips1, *aips2;
217 #ifdef AIPS3_CONFIG_BASE_ADDR
218 struct aipstz_regs *aips3;
220 aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR;
221 aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;
222 #ifdef AIPS3_CONFIG_BASE_ADDR
223 aips3 = (struct aipstz_regs *)AIPS3_CONFIG_BASE_ADDR;
227 * Set all MPROTx to be non-bufferable, trusted for R/W,
228 * not forced to user-mode.
230 writel(0x77777777, &aips1->mprot0);
231 writel(0x77777777, &aips1->mprot1);
232 writel(0x77777777, &aips2->mprot0);
233 writel(0x77777777, &aips2->mprot1);
236 * Set all OPACRx to be non-bufferable, not require
237 * supervisor privilege level for access,allow for
238 * write access and untrusted master access.
240 writel(0x00000000, &aips1->opacr0);
241 writel(0x00000000, &aips1->opacr1);
242 writel(0x00000000, &aips1->opacr2);
243 writel(0x00000000, &aips1->opacr3);
244 writel(0x00000000, &aips1->opacr4);
245 writel(0x00000000, &aips2->opacr0);
246 writel(0x00000000, &aips2->opacr1);
247 writel(0x00000000, &aips2->opacr2);
248 writel(0x00000000, &aips2->opacr3);
249 writel(0x00000000, &aips2->opacr4);
251 #ifdef AIPS3_CONFIG_BASE_ADDR
253 * Set all MPROTx to be non-bufferable, trusted for R/W,
254 * not forced to user-mode.
256 writel(0x77777777, &aips3->mprot0);
257 writel(0x77777777, &aips3->mprot1);
260 * Set all OPACRx to be non-bufferable, not require
261 * supervisor privilege level for access,allow for
262 * write access and untrusted master access.
264 writel(0x00000000, &aips3->opacr0);
265 writel(0x00000000, &aips3->opacr1);
266 writel(0x00000000, &aips3->opacr2);
267 writel(0x00000000, &aips3->opacr3);
268 writel(0x00000000, &aips3->opacr4);
272 static void clear_ldo_ramp(void)
274 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
277 /* ROM may modify LDO ramp up time according to fuse setting, so in
278 * order to be in the safe side we neeed to reset these settings to
279 * match the reset value: 0'b00
281 reg = readl(&anatop->ana_misc2);
282 reg &= ~(0x3f << 24);
283 writel(reg, &anatop->ana_misc2);
287 * Set the PMU_REG_CORE register
289 * Set LDO_SOC/PU/ARM regulators to the specified millivolt level.
290 * Possible values are from 0.725V to 1.450V in steps of
293 static int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
295 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
296 u32 val, step, old, reg = readl(&anatop->reg_core);
300 val = 0x00; /* Power gated off */
302 val = 0x1F; /* Power FET switched full on. No regulation */
304 val = (mv - 700) / 25;
322 old = (reg & (0x1F << shift)) >> shift;
323 step = abs(val - old);
327 reg = (reg & ~(0x1F << shift)) | (val << shift);
328 writel(reg, &anatop->reg_core);
331 * The LDO ramp-up is based on 64 clock cycles of 24 MHz = 2.6 us per
339 int check_cpu_temperature(int boot)
342 static int __data max_temp;
343 int boot_limit = getenv_ulong("max_boot_temp", 10, TEMPERATURE_HOT);
348 if (uclass_get_device_by_name(UCLASS_THERMAL, "imx_thermal", &dev)) {
350 printf("No thermal device found; cannot read CPU temperature\n");
356 ret = thermal_get_temp(dev, &tmp);
358 printf("Failed to read temperature: %d\n", ret);
359 return TEMPERATURE_MAX;
361 if (tmp < TEMPERATURE_MIN || tmp > TEMPERATURE_MAX) {
362 printf("Temperature: can't get valid data!\n");
367 if (tmp > boot_limit) {
368 printf("CPU is %d C; too hot, resetting...\n", tmp);
372 if (tmp > max_temp) {
373 if (tmp > boot_limit - TEMP_WARN_THRESHOLD)
374 printf("WARNING: CPU temperature %d C\n", tmp);
378 while (tmp >= boot_limit) {
380 printf("CPU is %d C; too hot to boot, waiting...\n",
387 ret = thermal_get_temp(dev, &tmp);
389 printf("Failed to read temperature: %d\n", ret);
390 return TEMPERATURE_MAX;
392 if (tmp > boot_limit - TEMP_WARN_THRESHOLD && tmp != max_temp)
393 printf("WARNING: CPU temperature %d C\n", tmp);
400 static void imx_set_wdog_powerdown(bool enable)
402 struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
403 struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
404 struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR;
406 if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) ||
407 is_cpu_type(MXC_CPU_MX6ULL))
408 writew(enable, &wdog3->wmcr);
410 /* Write to the PDE (Power Down Enable) bit */
411 writew(enable, &wdog1->wmcr);
412 writew(enable, &wdog2->wmcr);
415 static void set_ahb_rate(u32 val)
417 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
420 div = get_periph_clk() / val - 1;
421 reg = readl(&mxc_ccm->cbcdr);
423 writel((reg & (~MXC_CCM_CBCDR_AHB_PODF_MASK)) |
424 (div << MXC_CCM_CBCDR_AHB_PODF_OFFSET), &mxc_ccm->cbcdr);
427 static void clear_mmdc_ch_mask(void)
429 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
431 reg = readl(&mxc_ccm->ccdr);
433 /* Clear MMDC channel mask */
434 reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK);
435 writel(reg, &mxc_ccm->ccdr);
438 static void init_bandgap(void)
440 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
442 * Ensure the bandgap has stabilized.
444 while (!(readl(&anatop->ana_misc0) & 0x80))
447 * For best noise performance of the analog blocks using the
448 * outputs of the bandgap, the reftop_selfbiasoff bit should
451 writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_set);
454 #ifdef CONFIG_SOC_MX6SL
455 static void set_preclk_from_osc(void)
457 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
460 reg = readl(&mxc_ccm->cscmr1);
461 reg |= MXC_CCM_CSCMR1_PER_CLK_SEL_MASK;
462 writel(reg, &mxc_ccm->cscmr1);
466 #define SRC_SCR_WARM_RESET_ENABLE 0
468 static void init_src(void)
470 struct src *src_regs = (struct src *)SRC_BASE_ADDR;
474 * force warm reset sources to generate cold reset
475 * for a more reliable restart
477 val = readl(&src_regs->scr);
478 val &= ~(1 << SRC_SCR_WARM_RESET_ENABLE);
479 writel(val, &src_regs->scr);
482 int arch_cpu_init(void)
486 /* Need to clear MMDC_CHx_MASK to make warm reset work. */
487 clear_mmdc_ch_mask();
490 * Disable self-bias circuit in the analog bandap.
491 * The self-bias circuit is used by the bandgap during startup.
492 * This bit should be set after the bandgap has initialized.
497 * When low freq boot is enabled, ROM will not set AHB
498 * freq, so we need to ensure AHB freq is 132MHz in such
501 if (mxc_get_clock(MXC_ARM_CLK) == 396000000)
502 set_ahb_rate(132000000);
504 /* Set perclk to source from OSC 24MHz */
505 #if defined(CONFIG_SOC_MX6SL)
506 set_preclk_from_osc();
509 imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
511 #ifdef CONFIG_VIDEO_IPUV3
512 gd->arch.ipu_hw_rev = IPUV3_HW_REV_IPUV3H;
514 #ifdef CONFIG_APBH_DMA
515 /* Timer is required for Initializing APBH DMA */
525 int board_postclk_init(void)
527 set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */
532 #ifndef CONFIG_SYS_DCACHE_OFF
533 void enable_caches(void)
535 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
536 enum dcache_option option = DCACHE_WRITETHROUGH;
538 enum dcache_option option = DCACHE_WRITEBACK;
541 /* Avoid random hang when download by usb */
542 invalidate_dcache_all();
544 /* Enable D-cache. I-cache is already enabled in start.S */
547 /* Enable caching on OCRAM and ROM */
548 mmu_set_region_dcache_behaviour(ROMCP_ARB_BASE_ADDR,
551 mmu_set_region_dcache_behaviour(IRAM_BASE_ADDR,
557 #if defined(CONFIG_FEC_MXC)
558 __weak void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
560 unsigned int mac0, mac1;
563 if (dev_id < 0 || dev_id > 2)
566 if (fuse_read(4, 2, &mac0)) {
567 printf("Failed to read MAC0 fuse\n");
570 if (fuse_read(4, 3, &mac1)) {
571 printf("Failed to read MAC1 fuse\n");
587 //void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) __attribute__((weak("__imx_get_mac_from_fuse")));
590 void boot_mode_apply(unsigned cfg_val)
593 struct src *psrc = (struct src *)SRC_BASE_ADDR;
594 writel(cfg_val, &psrc->gpr9);
595 reg = readl(&psrc->gpr10);
600 writel(reg, &psrc->gpr10);
603 * cfg_val will be used for
604 * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
605 * After reset, if GPR10[28] is 1, ROM will use GPR9[25:0]
606 * instead of SBMR1 to determine the boot device.
608 const struct boot_mode soc_boot_modes[] = {
609 {"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
610 /* reserved value should start rom usb */
611 {"usb", MAKE_CFGVAL(0x01, 0x00, 0x00, 0x00)},
612 {"sata", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
613 {"ecspi1:0", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)},
614 {"ecspi1:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)},
615 {"ecspi1:2", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)},
616 {"ecspi1:3", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)},
617 /* 4 bit bus width */
618 {"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
619 {"esdhc2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
620 {"esdhc3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
621 {"esdhc4", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
627 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
628 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
631 u32 reg, periph1, periph2;
633 if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) ||
634 is_cpu_type(MXC_CPU_MX6ULL))
637 /* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
638 * to make sure PFD is working right, otherwise, PFDs may
639 * not output clock after reset, MX6DL and MX6SL have added 396M pfd
640 * workaround in ROM code, as bus clock need it
643 mask480 = ANATOP_PFD_CLKGATE_MASK(0) |
644 ANATOP_PFD_CLKGATE_MASK(1) |
645 ANATOP_PFD_CLKGATE_MASK(2) |
646 ANATOP_PFD_CLKGATE_MASK(3);
647 mask528 = ANATOP_PFD_CLKGATE_MASK(1) |
648 ANATOP_PFD_CLKGATE_MASK(3);
650 reg = readl(&ccm->cbcmr);
651 periph2 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK)
652 >> MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET);
653 periph1 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)
654 >> MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET);
656 /* Checking if PLL2 PFD0 or PLL2 PFD2 is using for periph clock */
657 if ((periph2 != 0x2) && (periph1 != 0x2))
658 mask528 |= ANATOP_PFD_CLKGATE_MASK(0);
660 if ((periph2 != 0x1) && (periph1 != 0x1) &&
661 (periph2 != 0x3) && (periph1 != 0x3))
662 mask528 |= ANATOP_PFD_CLKGATE_MASK(2);
664 writel(mask480, &anatop->pfd_480_set);
665 writel(mask528, &anatop->pfd_528_set);
666 writel(mask480, &anatop->pfd_480_clr);
667 writel(mask528, &anatop->pfd_528_clr);
670 #ifdef CONFIG_IMX_HDMI
671 void imx_enable_hdmi_phy(void)
673 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
675 reg = readb(&hdmi->phy_conf0);
676 reg |= HDMI_PHY_CONF0_PDZ_MASK;
677 writeb(reg, &hdmi->phy_conf0);
679 reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
680 writeb(reg, &hdmi->phy_conf0);
682 reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
683 writeb(reg, &hdmi->phy_conf0);
684 writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
687 void imx_setup_hdmi(void)
689 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
690 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
693 /* Turn on HDMI PHY clock */
694 reg = readl(&mxc_ccm->CCGR2);
695 reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK|
696 MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
697 writel(reg, &mxc_ccm->CCGR2);
698 writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
699 reg = readl(&mxc_ccm->chsccdr);
700 reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK|
701 MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK|
702 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
703 reg |= (CHSCCDR_PODF_DIVIDE_BY_3
704 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
705 |(CHSCCDR_IPU_PRE_CLK_540M_PFD
706 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
707 writel(reg, &mxc_ccm->chsccdr);
711 #ifndef CONFIG_SYS_L2CACHE_OFF
712 #define IOMUXC_GPR11_L2CACHE_AS_OCRAM 0x00000002
713 void v7_outer_cache_enable(void)
715 struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
720 * Set bit 22 in the auxiliary control register. If this bit
721 * is cleared, PL310 treats Normal Shared Non-cacheable
722 * accesses as Cacheable no-allocate.
724 setbits_le32(&pl310->pl310_aux_ctrl, L310_SHARED_ATT_OVERRIDE_ENABLE);
726 #if defined CONFIG_SOC_MX6SL
727 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
728 val = readl(&iomux->gpr[11]);
729 if (val & IOMUXC_GPR11_L2CACHE_AS_OCRAM) {
730 /* L2 cache configured as OCRAM, reset it */
731 val &= ~IOMUXC_GPR11_L2CACHE_AS_OCRAM;
732 writel(val, &iomux->gpr[11]);
736 /* Must disable the L2 before changing the latency parameters */
737 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
739 writel(0x132, &pl310->pl310_tag_latency_ctrl);
740 writel(0x132, &pl310->pl310_data_latency_ctrl);
742 val = readl(&pl310->pl310_prefetch_ctrl);
744 /* Turn on the L2 I/D prefetch */
748 * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0
749 * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2
750 * But according to ARM PL310 errata: 752271
751 * ID: 752271: Double linefill feature can cause data corruption
752 * Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2
753 * Workaround: The only workaround to this erratum is to disable the
754 * double linefill feature. This is the default behavior.
757 #ifndef CONFIG_SOC_MX6Q
760 writel(val, &pl310->pl310_prefetch_ctrl);
762 val = readl(&pl310->pl310_power_ctrl);
763 val |= L2X0_DYNAMIC_CLK_GATING_EN;
764 val |= L2X0_STNDBY_MODE_EN;
765 writel(val, &pl310->pl310_power_ctrl);
767 setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
770 void v7_outer_cache_disable(void)
772 struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
774 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
776 #endif /* !CONFIG_SYS_L2CACHE_OFF */