3 * Sascha Hauer, Pengutronix
5 * (C) Copyright 2009 Freescale Semiconductor, Inc.
7 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/errno.h>
13 #include <asm/arch/imx-regs.h>
14 #include <asm/arch/clock.h>
15 #include <asm/arch/sys_proto.h>
16 #include <asm/imx-common/boot_mode.h>
17 #include <asm/imx-common/dma.h>
19 #include <asm/arch/mxc_hdmi.h>
20 #include <asm/arch/crm_regs.h>
38 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
39 u32 reg = readl(&anatop->digprog_sololite);
40 u32 type = ((reg >> 16) & 0xff);
42 if (type != MXC_CPU_MX6SL) {
43 reg = readl(&anatop->digprog);
44 struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
45 u32 cfg = readl(&scu->config) & 3;
46 type = ((reg >> 16) & 0xff);
47 if (type == MXC_CPU_MX6DL) {
49 type = MXC_CPU_MX6SOLO;
52 if (type == MXC_CPU_MX6Q) {
58 reg &= 0xff; /* mx6 silicon revision */
59 return (type << 12) | (reg + 0x10);
62 #ifdef CONFIG_REVISION_TAG
63 u32 __weak get_board_rev(void)
65 u32 cpurev = get_cpu_rev();
66 u32 type = ((cpurev >> 12) & 0xff);
67 if (type == MXC_CPU_MX6SOLO)
68 cpurev = (MXC_CPU_MX6DL) << 12 | (cpurev & 0xFFF);
70 if (type == MXC_CPU_MX6D)
71 cpurev = (MXC_CPU_MX6Q) << 12 | (cpurev & 0xFFF);
79 struct aipstz_regs *aips1, *aips2;
81 aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR;
82 aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;
85 * Set all MPROTx to be non-bufferable, trusted for R/W,
86 * not forced to user-mode.
88 writel(0x77777777, &aips1->mprot0);
89 writel(0x77777777, &aips1->mprot1);
90 writel(0x77777777, &aips2->mprot0);
91 writel(0x77777777, &aips2->mprot1);
94 * Set all OPACRx to be non-bufferable, not require
95 * supervisor privilege level for access,allow for
96 * write access and untrusted master access.
98 writel(0x00000000, &aips1->opacr0);
99 writel(0x00000000, &aips1->opacr1);
100 writel(0x00000000, &aips1->opacr2);
101 writel(0x00000000, &aips1->opacr3);
102 writel(0x00000000, &aips1->opacr4);
103 writel(0x00000000, &aips2->opacr0);
104 writel(0x00000000, &aips2->opacr1);
105 writel(0x00000000, &aips2->opacr2);
106 writel(0x00000000, &aips2->opacr3);
107 writel(0x00000000, &aips2->opacr4);
110 static void clear_ldo_ramp(void)
112 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
115 /* ROM may modify LDO ramp up time according to fuse setting, so in
116 * order to be in the safe side we neeed to reset these settings to
117 * match the reset value: 0'b00
119 reg = readl(&anatop->ana_misc2);
120 reg &= ~(0x3f << 24);
121 writel(reg, &anatop->ana_misc2);
127 * Mask out the REG_CORE[22:18] bits (REG2_TRIG) and set
128 * them to the specified millivolt level.
129 * Possible values are from 0.725V to 1.450V in steps of
132 static int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
134 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
135 u32 val, step, old, reg = readl(&anatop->reg_core);
139 val = 0x00; /* Power gated off */
141 val = 0x1F; /* Power FET switched full on. No regulation */
143 val = (mv - 700) / 25;
161 old = (reg & (0x1F << shift)) >> shift;
162 step = abs(val - old);
166 reg = (reg & ~(0x1F << shift)) | (val << shift);
167 writel(reg, &anatop->reg_core);
170 * The LDO ramp-up is based on 64 clock cycles of 24 MHz = 2.6 us per
178 static void imx_set_wdog_powerdown(bool enable)
180 struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
181 struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
183 /* Write to the PDE (Power Down Enable) bit */
184 writew(enable, &wdog1->wmcr);
185 writew(enable, &wdog2->wmcr);
188 static void set_ahb_rate(u32 val)
190 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
193 div = get_periph_clk() / val - 1;
194 reg = readl(&mxc_ccm->cbcdr);
196 writel((reg & (~MXC_CCM_CBCDR_AHB_PODF_MASK)) |
197 (div << MXC_CCM_CBCDR_AHB_PODF_OFFSET), &mxc_ccm->cbcdr);
200 static void clear_mmdc_ch_mask(void)
202 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
204 /* Clear MMDC channel mask */
205 writel(0, &mxc_ccm->ccdr);
208 int arch_cpu_init(void)
212 /* Need to clear MMDC_CHx_MASK to make warm reset work. */
213 clear_mmdc_ch_mask();
216 * When low freq boot is enabled, ROM will not set AHB
217 * freq, so we need to ensure AHB freq is 132MHz in such
220 if (mxc_get_clock(MXC_ARM_CLK) == 396000000)
221 set_ahb_rate(132000000);
223 imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
225 #ifdef CONFIG_APBH_DMA
233 int board_postclk_init(void)
235 set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */
240 #ifndef CONFIG_SYS_DCACHE_OFF
241 void enable_caches(void)
243 /* Avoid random hang when download by usb */
244 invalidate_dcache_all();
245 /* Enable D-cache. I-cache is already enabled in start.S */
250 #if defined(CONFIG_FEC_MXC)
251 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
253 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
254 struct fuse_bank *bank = &ocotp->bank[4];
255 struct fuse_bank4_regs *fuse =
256 (struct fuse_bank4_regs *)bank->fuse_regs;
258 u32 value = readl(&fuse->mac_addr_high);
259 mac[0] = (value >> 8);
262 value = readl(&fuse->mac_addr_low);
263 mac[2] = value >> 24 ;
264 mac[3] = value >> 16 ;
265 mac[4] = value >> 8 ;
271 void boot_mode_apply(unsigned cfg_val)
274 struct src *psrc = (struct src *)SRC_BASE_ADDR;
275 writel(cfg_val, &psrc->gpr9);
276 reg = readl(&psrc->gpr10);
281 writel(reg, &psrc->gpr10);
284 * cfg_val will be used for
285 * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
286 * After reset, if GPR10[28] is 1, ROM will copy GPR9[25:0]
287 * to SBMR1, which will determine the boot device.
289 const struct boot_mode soc_boot_modes[] = {
290 {"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
291 /* reserved value should start rom usb */
292 {"usb", MAKE_CFGVAL(0x01, 0x00, 0x00, 0x00)},
293 {"sata", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
294 {"escpi1:0", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)},
295 {"escpi1:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)},
296 {"escpi1:2", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)},
297 {"escpi1:3", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)},
298 /* 4 bit bus width */
299 {"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
300 {"esdhc2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
301 {"esdhc3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
302 {"esdhc4", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
308 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
309 int is_6q = is_cpu_type(MXC_CPU_MX6Q);
313 /* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
314 * to make sure PFD is working right, otherwise, PFDs may
315 * not output clock after reset, MX6DL and MX6SL have added 396M pfd
316 * workaround in ROM code, as bus clock need it
319 mask480 = ANATOP_PFD_CLKGATE_MASK(0) |
320 ANATOP_PFD_CLKGATE_MASK(1) |
321 ANATOP_PFD_CLKGATE_MASK(2) |
322 ANATOP_PFD_CLKGATE_MASK(3);
323 mask528 = ANATOP_PFD_CLKGATE_MASK(0) |
324 ANATOP_PFD_CLKGATE_MASK(1) |
325 ANATOP_PFD_CLKGATE_MASK(3);
328 * Don't reset PFD2 on DL/S
331 mask528 |= ANATOP_PFD_CLKGATE_MASK(2);
332 writel(mask480, &anatop->pfd_480_set);
333 writel(mask528, &anatop->pfd_528_set);
334 writel(mask480, &anatop->pfd_480_clr);
335 writel(mask528, &anatop->pfd_528_clr);
338 #ifdef CONFIG_IMX_HDMI
339 void imx_enable_hdmi_phy(void)
341 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
343 reg = readb(&hdmi->phy_conf0);
344 reg |= HDMI_PHY_CONF0_PDZ_MASK;
345 writeb(reg, &hdmi->phy_conf0);
347 reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
348 writeb(reg, &hdmi->phy_conf0);
350 reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
351 writeb(reg, &hdmi->phy_conf0);
352 writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
355 void imx_setup_hdmi(void)
357 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
358 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
361 /* Turn on HDMI PHY clock */
362 reg = readl(&mxc_ccm->CCGR2);
363 reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK|
364 MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
365 writel(reg, &mxc_ccm->CCGR2);
366 writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
367 reg = readl(&mxc_ccm->chsccdr);
368 reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK|
369 MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK|
370 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
371 reg |= (CHSCCDR_PODF_DIVIDE_BY_3
372 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
373 |(CHSCCDR_IPU_PRE_CLK_540M_PFD
374 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
375 writel(reg, &mxc_ccm->chsccdr);