3 * Sascha Hauer, Pengutronix
5 * (C) Copyright 2009 Freescale Semiconductor, Inc.
7 * SPDX-License-Identifier: GPL-2.0+
15 #include <imx_thermal.h>
16 #include <asm/armv7.h>
17 #include <asm/bootm.h>
18 #include <asm/pl310.h>
19 #include <asm/errno.h>
21 #include <asm/arch/imx-regs.h>
22 #include <asm/arch/crm_regs.h>
23 #include <asm/arch/regs-ocotp.h>
24 #include <asm/arch/clock.h>
25 #include <asm/arch/mxc_hdmi.h>
26 #include <asm/arch/sys_proto.h>
27 #include <asm/imx-common/boot_mode.h>
28 #include <asm/imx-common/dma.h>
30 DECLARE_GLOBAL_DATA_PTR;
32 #define __data __attribute__((section(".data")))
34 #ifdef CONFIG_MX6_TEMPERATURE_MIN
35 #define TEMPERATURE_MIN CONFIG_MX6_TEMPERATURE_MIN
37 #define TEMPERATURE_MIN (-40)
39 #ifdef CONFIG_MX6_TEMPERATURE_HOT
40 #define TEMPERATURE_HOT CONFIG_MX6_TEMPERATURE_HOT
42 #define TEMPERATURE_HOT 80
44 #ifdef CONFIG_MX6_TEMPERATURE_MAX
45 #define TEMPERATURE_MAX CONFIG_MX6_TEMPERATURE_MAX
47 #define TEMPERATURE_MAX 125
49 #define TEMP_AVG_COUNT 5
50 #define TEMP_WARN_THRESHOLD 5
66 #if defined(CONFIG_IMX6_THERMAL)
67 static const struct imx_thermal_plat imx6_thermal_plat = {
68 .regs = (void *)ANATOP_BASE_ADDR,
73 U_BOOT_DEVICE(imx6_thermal) = {
74 .name = "imx_thermal",
75 .platdata = &imx6_thermal_plat,
81 struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
82 return readl(&scu->config) & 3;
87 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
88 u32 reg = readl(&anatop->digprog_sololite);
89 u32 type = ((reg >> 16) & 0xff);
91 if (type != MXC_CPU_MX6SL) {
92 reg = readl(&anatop->digprog);
93 struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
94 u32 cfg = readl(&scu->config) & 3;
95 type = ((reg >> 16) & 0xff);
96 if (type == MXC_CPU_MX6DL) {
98 type = MXC_CPU_MX6SOLO;
101 if (type == MXC_CPU_MX6Q) {
107 reg &= 0xff; /* mx6 silicon revision */
108 return (type << 12) | (reg + 0x10);
112 * OCOTP_CFG3[17:16] (see Fusemap Description Table offset 0x440)
113 * defines a 2-bit SPEED_GRADING
115 #define OCOTP_CFG3_SPEED_SHIFT 16
116 #define OCOTP_CFG3_SPEED_800MHZ 0
117 #define OCOTP_CFG3_SPEED_850MHZ 1
118 #define OCOTP_CFG3_SPEED_1GHZ 2
119 #define OCOTP_CFG3_SPEED_1P2GHZ 3
121 u32 get_cpu_speed_grade_hz(void)
123 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
124 struct fuse_bank *bank = &ocotp->bank[0];
125 struct fuse_bank0_regs *fuse =
126 (struct fuse_bank0_regs *)bank->fuse_regs;
129 val = readl(&fuse->cfg3);
130 val >>= OCOTP_CFG3_SPEED_SHIFT;
134 /* Valid for IMX6DQ */
135 case OCOTP_CFG3_SPEED_1P2GHZ:
136 if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
138 /* Valid for IMX6SX/IMX6SDL/IMX6DQ */
139 case OCOTP_CFG3_SPEED_1GHZ:
141 /* Valid for IMX6DQ */
142 case OCOTP_CFG3_SPEED_850MHZ:
143 if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
145 /* Valid for IMX6SX/IMX6SDL/IMX6DQ */
146 case OCOTP_CFG3_SPEED_800MHZ:
153 * OCOTP_MEM0[7:6] (see Fusemap Description Table offset 0x480)
154 * defines a 2-bit Temperature Grade
156 * return temperature grade and min/max temperature in celcius
158 #define OCOTP_MEM0_TEMP_SHIFT 6
160 u32 get_cpu_temp_grade(int *minc, int *maxc)
162 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
163 struct fuse_bank *bank = &ocotp->bank[1];
164 struct fuse_bank1_regs *fuse =
165 (struct fuse_bank1_regs *)bank->fuse_regs;
168 val = readl(&fuse->mem0);
169 val >>= OCOTP_MEM0_TEMP_SHIFT;
173 if (val == TEMP_AUTOMOTIVE) {
176 } else if (val == TEMP_INDUSTRIAL) {
179 } else if (val == TEMP_EXTCOMMERCIAL) {
190 #ifdef CONFIG_REVISION_TAG
191 u32 __weak get_board_rev(void)
193 u32 cpurev = get_cpu_rev();
194 u32 type = ((cpurev >> 12) & 0xff);
195 if (type == MXC_CPU_MX6SOLO)
196 cpurev = (MXC_CPU_MX6DL) << 12 | (cpurev & 0xFFF);
198 if (type == MXC_CPU_MX6D)
199 cpurev = (MXC_CPU_MX6Q) << 12 | (cpurev & 0xFFF);
207 struct aipstz_regs *aips1, *aips2;
208 #ifdef CONFIG_SOC_MX6SX
209 struct aipstz_regs *aips3;
212 aips1 = (struct aipstz_regs *)AIPS1_ARB_BASE_ADDR;
213 aips2 = (struct aipstz_regs *)AIPS2_ARB_BASE_ADDR;
214 #ifdef CONFIG_SOC_MX6SX
215 aips3 = (struct aipstz_regs *)AIPS3_ARB_BASE_ADDR;
219 * Set all MPROTx to be non-bufferable, trusted for R/W,
220 * not forced to user-mode.
222 writel(0x77777777, &aips1->mprot0);
223 writel(0x77777777, &aips1->mprot1);
224 writel(0x77777777, &aips2->mprot0);
225 writel(0x77777777, &aips2->mprot1);
228 * Set all OPACRx to be non-bufferable, not require
229 * supervisor privilege level for access,allow for
230 * write access and untrusted master access.
232 writel(0x00000000, &aips1->opacr0);
233 writel(0x00000000, &aips1->opacr1);
234 writel(0x00000000, &aips1->opacr2);
235 writel(0x00000000, &aips1->opacr3);
236 writel(0x00000000, &aips1->opacr4);
237 writel(0x00000000, &aips2->opacr0);
238 writel(0x00000000, &aips2->opacr1);
239 writel(0x00000000, &aips2->opacr2);
240 writel(0x00000000, &aips2->opacr3);
241 writel(0x00000000, &aips2->opacr4);
243 #ifdef CONFIG_SOC_MX6SX
245 * Set all MPROTx to be non-bufferable, trusted for R/W,
246 * not forced to user-mode.
248 writel(0x77777777, &aips3->mprot0);
249 writel(0x77777777, &aips3->mprot1);
252 * Set all OPACRx to be non-bufferable, not require
253 * supervisor privilege level for access,allow for
254 * write access and untrusted master access.
256 writel(0x00000000, &aips3->opacr0);
257 writel(0x00000000, &aips3->opacr1);
258 writel(0x00000000, &aips3->opacr2);
259 writel(0x00000000, &aips3->opacr3);
260 writel(0x00000000, &aips3->opacr4);
264 static void clear_ldo_ramp(void)
266 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
269 /* ROM may modify LDO ramp up time according to fuse setting, so in
270 * order to be in the safe side we neeed to reset these settings to
271 * match the reset value: 0'b00
273 reg = readl(&anatop->ana_misc2);
274 reg &= ~(0x3f << 24);
275 writel(reg, &anatop->ana_misc2);
279 * Set the PMU_REG_CORE register
281 * Set LDO_SOC/PU/ARM regulators to the specified millivolt level.
282 * Possible values are from 0.725V to 1.450V in steps of
285 static int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
287 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
288 u32 val, step, old, reg = readl(&anatop->reg_core);
292 val = 0x00; /* Power gated off */
294 val = 0x1F; /* Power FET switched full on. No regulation */
296 val = (mv - 700) / 25;
314 old = (reg & (0x1F << shift)) >> shift;
315 step = abs(val - old);
319 reg = (reg & ~(0x1F << shift)) | (val << shift);
320 writel(reg, &anatop->reg_core);
323 * The LDO ramp-up is based on 64 clock cycles of 24 MHz = 2.6 us per
331 static u32 __data thermal_calib;
333 #define FACTOR0 10000000
334 #define FACTOR1 15976
335 #define FACTOR2 4297157
337 int raw_to_celsius(unsigned int raw, unsigned int raw_25c, unsigned int raw_hot,
338 unsigned int hot_temp)
342 if (raw_hot != 0 && hot_temp != 0) {
343 unsigned int raw_n40c, ratio;
345 ratio = ((raw_25c - raw_hot) * 100) / (hot_temp - 25);
346 raw_n40c = raw_25c + (13 * ratio) / 20;
348 temperature = (raw_n40c - raw) * 100 / ratio - 40;
350 temperature = TEMPERATURE_MIN;
352 u64 temp64 = FACTOR0;
355 * Derived from linear interpolation:
356 * slope = 0.4297157 - (0.0015976 * 25C fuse)
357 * slope = (FACTOR2 - FACTOR1 * n1) / FACTOR0
358 * (Nmeas - n1) / (Tmeas - t1) = slope
359 * We want to reduce this down to the minimum computation necessary
360 * for each temperature read. Also, we want Tmeas in millicelsius
361 * and we don't want to lose precision from integer division. So...
362 * Tmeas = (Nmeas - n1) / slope + t1
363 * milli_Tmeas = 1000 * (Nmeas - n1) / slope + 1000 * t1
364 * milli_Tmeas = -1000 * (n1 - Nmeas) / slope + 1000 * t1
365 * Let constant c1 = (-1000 / slope)
366 * milli_Tmeas = (n1 - Nmeas) * c1 + 1000 * t1
367 * Let constant c2 = n1 *c1 + 1000 * t1
368 * milli_Tmeas = c2 - Nmeas * c1
371 do_div(temp64, FACTOR1 * raw_25c - FACTOR2);
373 c2 = raw_25c * c1 + 1000 * 25;
374 temperature = (c2 - raw * c1) / 1000;
379 int read_cpu_temperature(void)
381 unsigned int reg, tmp, i;
382 unsigned int raw_25c, raw_hot, hot_temp;
384 struct anatop_regs *const anatop = (void *)ANATOP_BASE_ADDR;
385 struct mx6_ocotp_regs *const ocotp_regs = (void *)OCOTP_BASE_ADDR;
387 if (!thermal_calib) {
389 writel(1, &ocotp_regs->hw_ocotp_read_ctrl);
390 thermal_calib = readl(&ocotp_regs->hw_ocotp_ana1);
391 writel(0, &ocotp_regs->hw_ocotp_read_ctrl);
395 if (thermal_calib == 0 || thermal_calib == 0xffffffff)
396 return TEMPERATURE_MIN;
399 * [31:20] sensor value @ 25C
400 * [19:8] sensor value of hot
401 * [7:0] hot temperature value */
402 raw_25c = thermal_calib >> 20;
403 raw_hot = (thermal_calib & 0xfff00) >> 8;
404 hot_temp = thermal_calib & 0xff;
406 /* now we only using single measure, every time we measure
407 * the temperature, we will power on/off the anadig module
409 writel(BM_ANADIG_TEMPSENSE0_POWER_DOWN, &anatop->tempsense0_clr);
410 writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_set);
412 /* write measure freq */
413 writel(327, &anatop->tempsense1);
414 writel(BM_ANADIG_TEMPSENSE0_MEASURE_TEMP, &anatop->tempsense0_clr);
415 writel(BM_ANADIG_TEMPSENSE0_FINISHED, &anatop->tempsense0_clr);
416 writel(BM_ANADIG_TEMPSENSE0_MEASURE_TEMP, &anatop->tempsense0_set);
418 /* average the temperature value over multiple readings */
419 for (i = 0; i < TEMP_AVG_COUNT; i++) {
423 while ((readl(&anatop->tempsense0) &
424 BM_ANADIG_TEMPSENSE0_FINISHED) == 0) {
429 if ((readl(&anatop->tempsense0) &
430 BM_ANADIG_TEMPSENSE0_FINISHED) == 0) {
432 printf("Failed to read temp sensor\n");
438 reg = (readl(&anatop->tempsense0) &
439 BM_ANADIG_TEMPSENSE0_TEMP_VALUE) >>
440 BP_ANADIG_TEMPSENSE0_TEMP_VALUE;
444 tmp = (tmp * i + reg) / (i + 1);
445 writel(BM_ANADIG_TEMPSENSE0_FINISHED,
446 &anatop->tempsense0_clr);
449 temperature = raw_to_celsius(tmp, raw_25c, raw_hot, hot_temp);
451 /* power down anatop thermal sensor */
452 writel(BM_ANADIG_TEMPSENSE0_POWER_DOWN, &anatop->tempsense0_set);
453 writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_clr);
458 int check_cpu_temperature(int boot)
460 static int __data max_temp;
461 int boot_limit = getenv_ulong("max_boot_temp", 10, TEMPERATURE_HOT);
462 int tmp = read_cpu_temperature();
465 if (tmp < TEMPERATURE_MIN || tmp > TEMPERATURE_MAX) {
466 printf("Temperature: can't get valid data!\n");
471 if (tmp > boot_limit) {
472 printf("CPU is %d C, too hot, resetting...\n", tmp);
476 if (tmp > max_temp) {
477 if (tmp > boot_limit - TEMP_WARN_THRESHOLD)
478 printf("WARNING: CPU temperature %d C\n", tmp);
482 printf("Temperature: %d C, calibration data 0x%x\n",
484 while (tmp >= boot_limit) {
486 printf("CPU is %d C, too hot to boot, waiting...\n",
493 tmp = read_cpu_temperature();
494 if (tmp > boot_limit - TEMP_WARN_THRESHOLD && tmp != max_temp)
495 printf("WARNING: CPU temperature %d C\n", tmp);
502 static void imx_set_wdog_powerdown(bool enable)
504 struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
505 struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
508 struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR;
509 writew(enable, &wdog3->wmcr);
512 /* Write to the PDE (Power Down Enable) bit */
513 writew(enable, &wdog1->wmcr);
514 writew(enable, &wdog2->wmcr);
517 static void set_ahb_rate(u32 val)
519 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
522 div = get_periph_clk() / val - 1;
523 reg = readl(&mxc_ccm->cbcdr);
525 writel((reg & (~MXC_CCM_CBCDR_AHB_PODF_MASK)) |
526 (div << MXC_CCM_CBCDR_AHB_PODF_OFFSET), &mxc_ccm->cbcdr);
529 static void clear_mmdc_ch_mask(void)
531 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
533 /* Clear MMDC channel mask */
534 writel(0, &mxc_ccm->ccdr);
537 static void init_bandgap(void)
539 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
541 * Ensure the bandgap has stabilized.
543 while (!(readl(&anatop->ana_misc0) & 0x80))
546 * For best noise performance of the analog blocks using the
547 * outputs of the bandgap, the reftop_selfbiasoff bit should
550 writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_set);
553 #ifdef CONFIG_SOC_MX6SL
554 static void set_preclk_from_osc(void)
556 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
559 reg = readl(&mxc_ccm->cscmr1);
560 reg |= MXC_CCM_CSCMR1_PER_CLK_SEL_MASK;
561 writel(reg, &mxc_ccm->cscmr1);
565 #define SRC_SCR_WARM_RESET_ENABLE 0
567 static void init_src(void)
569 struct src *src_regs = (struct src *)SRC_BASE_ADDR;
573 * force warm reset sources to generate cold reset
574 * for a more reliable restart
576 val = readl(&src_regs->scr);
577 val &= ~(1 << SRC_SCR_WARM_RESET_ENABLE);
578 writel(val, &src_regs->scr);
581 int arch_cpu_init(void)
585 /* Need to clear MMDC_CHx_MASK to make warm reset work. */
586 clear_mmdc_ch_mask();
589 * Disable self-bias circuit in the analog bandap.
590 * The self-bias circuit is used by the bandgap during startup.
591 * This bit should be set after the bandgap has initialized.
596 * When low freq boot is enabled, ROM will not set AHB
597 * freq, so we need to ensure AHB freq is 132MHz in such
600 if (mxc_get_clock(MXC_ARM_CLK) == 396000000)
601 set_ahb_rate(132000000);
603 /* Set perclk to source from OSC 24MHz */
604 #if defined(CONFIG_SOC_MX6SL)
605 set_preclk_from_osc();
608 imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
610 #ifdef CONFIG_VIDEO_IPUV3
611 gd->arch.ipu_hw_rev = IPUV3_HW_REV_IPUV3H;
613 #ifdef CONFIG_APBH_DMA
614 /* Timer is required for Initializing APBH DMA */
624 int board_postclk_init(void)
626 set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */
631 #ifndef CONFIG_SYS_DCACHE_OFF
632 void enable_caches(void)
634 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
635 enum dcache_option option = DCACHE_WRITETHROUGH;
637 enum dcache_option option = DCACHE_WRITEBACK;
640 /* Avoid random hang when download by usb */
641 invalidate_dcache_all();
643 /* Enable D-cache. I-cache is already enabled in start.S */
646 /* Enable caching on OCRAM and ROM */
647 mmu_set_region_dcache_behaviour(ROMCP_ARB_BASE_ADDR,
650 mmu_set_region_dcache_behaviour(IRAM_BASE_ADDR,
656 #if defined(CONFIG_FEC_MXC)
657 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
659 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
660 struct fuse_bank *bank = &ocotp->bank[4];
661 struct fuse_bank4_regs *fuse =
662 (struct fuse_bank4_regs *)bank->fuse_regs;
664 u32 value = readl(&fuse->mac_addr_high);
665 mac[0] = (value >> 8);
668 value = readl(&fuse->mac_addr_low);
669 mac[2] = value >> 24;
670 mac[3] = value >> 16;
676 void boot_mode_apply(unsigned cfg_val)
679 struct src *psrc = (struct src *)SRC_BASE_ADDR;
680 writel(cfg_val, &psrc->gpr9);
681 reg = readl(&psrc->gpr10);
686 writel(reg, &psrc->gpr10);
689 * cfg_val will be used for
690 * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
691 * After reset, if GPR10[28] is 1, ROM will use GPR9[25:0]
692 * instead of SBMR1 to determine the boot device.
694 const struct boot_mode soc_boot_modes[] = {
695 {"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
696 /* reserved value should start rom usb */
697 {"usb", MAKE_CFGVAL(0x01, 0x00, 0x00, 0x00)},
698 {"sata", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
699 {"ecspi1:0", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)},
700 {"ecspi1:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)},
701 {"ecspi1:2", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)},
702 {"ecspi1:3", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)},
703 /* 4 bit bus width */
704 {"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
705 {"esdhc2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
706 {"esdhc3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
707 {"esdhc4", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
713 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
714 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
717 u32 reg, periph1, periph2;
719 if (is_cpu_type(MXC_CPU_MX6SX))
722 /* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
723 * to make sure PFD is working right, otherwise, PFDs may
724 * not output clock after reset, MX6DL and MX6SL have added 396M pfd
725 * workaround in ROM code, as bus clock need it
728 mask480 = ANATOP_PFD_CLKGATE_MASK(0) |
729 ANATOP_PFD_CLKGATE_MASK(1) |
730 ANATOP_PFD_CLKGATE_MASK(2) |
731 ANATOP_PFD_CLKGATE_MASK(3);
732 mask528 = ANATOP_PFD_CLKGATE_MASK(1) |
733 ANATOP_PFD_CLKGATE_MASK(3);
735 reg = readl(&ccm->cbcmr);
736 periph2 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK)
737 >> MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET);
738 periph1 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)
739 >> MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET);
741 /* Checking if PLL2 PFD0 or PLL2 PFD2 is using for periph clock */
742 if ((periph2 != 0x2) && (periph1 != 0x2))
743 mask528 |= ANATOP_PFD_CLKGATE_MASK(0);
745 if ((periph2 != 0x1) && (periph1 != 0x1) &&
746 (periph2 != 0x3) && (periph1 != 0x3))
747 mask528 |= ANATOP_PFD_CLKGATE_MASK(2);
749 writel(mask480, &anatop->pfd_480_set);
750 writel(mask528, &anatop->pfd_528_set);
751 writel(mask480, &anatop->pfd_480_clr);
752 writel(mask528, &anatop->pfd_528_clr);
755 #ifdef CONFIG_IMX_HDMI
756 void imx_enable_hdmi_phy(void)
758 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
760 reg = readb(&hdmi->phy_conf0);
761 reg |= HDMI_PHY_CONF0_PDZ_MASK;
762 writeb(reg, &hdmi->phy_conf0);
764 reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
765 writeb(reg, &hdmi->phy_conf0);
767 reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
768 writeb(reg, &hdmi->phy_conf0);
769 writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
772 void imx_setup_hdmi(void)
774 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
775 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
778 /* Turn on HDMI PHY clock */
779 reg = readl(&mxc_ccm->CCGR2);
780 reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK|
781 MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
782 writel(reg, &mxc_ccm->CCGR2);
783 writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
784 reg = readl(&mxc_ccm->chsccdr);
785 reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK|
786 MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK|
787 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
788 reg |= (CHSCCDR_PODF_DIVIDE_BY_3
789 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
790 |(CHSCCDR_IPU_PRE_CLK_540M_PFD
791 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
792 writel(reg, &mxc_ccm->chsccdr);
796 #ifndef CONFIG_SYS_L2CACHE_OFF
797 #define IOMUXC_GPR11_L2CACHE_AS_OCRAM 0x00000002
798 void v7_outer_cache_enable(void)
800 struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
805 * Set bit 22 in the auxiliary control register. If this bit
806 * is cleared, PL310 treats Normal Shared Non-cacheable
807 * accesses as Cacheable no-allocate.
809 setbits_le32(&pl310->pl310_aux_ctrl, L310_SHARED_ATT_OVERRIDE_ENABLE);
811 #if defined CONFIG_SOC_MX6SL
812 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
813 val = readl(&iomux->gpr[11]);
814 if (val & IOMUXC_GPR11_L2CACHE_AS_OCRAM) {
815 /* L2 cache configured as OCRAM, reset it */
816 val &= ~IOMUXC_GPR11_L2CACHE_AS_OCRAM;
817 writel(val, &iomux->gpr[11]);
821 /* Must disable the L2 before changing the latency parameters */
822 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
824 writel(0x132, &pl310->pl310_tag_latency_ctrl);
825 writel(0x132, &pl310->pl310_data_latency_ctrl);
827 val = readl(&pl310->pl310_prefetch_ctrl);
829 /* Turn on the L2 I/D prefetch */
833 * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0
834 * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2
835 * But according to ARM PL310 errata: 752271
836 * ID: 752271: Double linefill feature can cause data corruption
837 * Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2
838 * Workaround: The only workaround to this erratum is to disable the
839 * double linefill feature. This is the default behavior.
842 #ifndef CONFIG_SOC_MX6Q
845 writel(val, &pl310->pl310_prefetch_ctrl);
847 val = readl(&pl310->pl310_power_ctrl);
848 val |= L2X0_DYNAMIC_CLK_GATING_EN;
849 val |= L2X0_STNDBY_MODE_EN;
850 writel(val, &pl310->pl310_power_ctrl);
852 setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
855 void v7_outer_cache_disable(void)
857 struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
859 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
861 #endif /* !CONFIG_SYS_L2CACHE_OFF */