3 * Sascha Hauer, Pengutronix
5 * (C) Copyright 2009 Freescale Semiconductor, Inc.
7 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/armv7.h>
12 #include <asm/bootm.h>
13 #include <asm/pl310.h>
14 #include <asm/errno.h>
16 #include <asm/arch/imx-regs.h>
17 #include <asm/arch/crm_regs.h>
18 #include <asm/arch/regs-ocotp.h>
19 #include <asm/arch/clock.h>
20 #include <asm/arch/sys_proto.h>
21 #include <asm/imx-common/boot_mode.h>
22 #include <asm/imx-common/dma.h>
24 #include <asm/arch/mxc_hdmi.h>
25 #include <asm/arch/crm_regs.h>
26 #include <asm/bootm.h>
28 #include <imx_thermal.h>
32 DECLARE_GLOBAL_DATA_PTR;
34 #define __data __attribute__((section(".data")))
36 #ifdef CONFIG_MX6_TEMPERATURE_MIN
37 #define TEMPERATURE_MIN CONFIG_MX6_TEMPERATURE_MIN
39 #define TEMPERATURE_MIN (-40)
41 #ifdef CONFIG_MX6_TEMPERATURE_HOT
42 #define TEMPERATURE_HOT CONFIG_MX6_TEMPERATURE_HOT
44 #define TEMPERATURE_HOT 80
46 #ifdef CONFIG_MX6_TEMPERATURE_MAX
47 #define TEMPERATURE_MAX CONFIG_MX6_TEMPERATURE_MAX
49 #define TEMPERATURE_MAX 125
51 #define TEMP_AVG_COUNT 5
52 #define TEMP_WARN_THRESHOLD 5
68 #if defined(CONFIG_IMX6_THERMAL)
69 static const struct imx_thermal_plat imx6_thermal_plat = {
70 .regs = (void *)ANATOP_BASE_ADDR,
75 U_BOOT_DEVICE(imx6_thermal) = {
76 .name = "imx_thermal",
77 .platdata = &imx6_thermal_plat,
83 struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
84 return readl(&scu->config) & 3;
89 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
90 u32 reg = readl(&anatop->digprog_sololite);
91 u32 type = ((reg >> 16) & 0xff);
93 if (type != MXC_CPU_MX6SL) {
94 reg = readl(&anatop->digprog);
95 struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
96 u32 cfg = readl(&scu->config) & 3;
97 type = ((reg >> 16) & 0xff);
98 if (type == MXC_CPU_MX6DL) {
100 type = MXC_CPU_MX6SOLO;
103 if (type == MXC_CPU_MX6Q) {
109 reg &= 0xff; /* mx6 silicon revision */
110 return (type << 12) | (reg + 0x10);
113 #ifdef CONFIG_REVISION_TAG
114 u32 __weak get_board_rev(void)
116 u32 cpurev = get_cpu_rev();
117 u32 type = ((cpurev >> 12) & 0xff);
118 if (type == MXC_CPU_MX6SOLO)
119 cpurev = (MXC_CPU_MX6DL) << 12 | (cpurev & 0xFFF);
121 if (type == MXC_CPU_MX6D)
122 cpurev = (MXC_CPU_MX6Q) << 12 | (cpurev & 0xFFF);
130 struct aipstz_regs *aips1, *aips2;
132 struct aipstz_regs *aips3;
135 aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR;
136 aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;
138 aips3 = (struct aipstz_regs *)AIPS3_BASE_ADDR;
142 * Set all MPROTx to be non-bufferable, trusted for R/W,
143 * not forced to user-mode.
145 writel(0x77777777, &aips1->mprot0);
146 writel(0x77777777, &aips1->mprot1);
147 writel(0x77777777, &aips2->mprot0);
148 writel(0x77777777, &aips2->mprot1);
151 * Set all OPACRx to be non-bufferable, not require
152 * supervisor privilege level for access,allow for
153 * write access and untrusted master access.
155 writel(0x00000000, &aips1->opacr0);
156 writel(0x00000000, &aips1->opacr1);
157 writel(0x00000000, &aips1->opacr2);
158 writel(0x00000000, &aips1->opacr3);
159 writel(0x00000000, &aips1->opacr4);
160 writel(0x00000000, &aips2->opacr0);
161 writel(0x00000000, &aips2->opacr1);
162 writel(0x00000000, &aips2->opacr2);
163 writel(0x00000000, &aips2->opacr3);
164 writel(0x00000000, &aips2->opacr4);
168 * Set all MPROTx to be non-bufferable, trusted for R/W,
169 * not forced to user-mode.
171 writel(0x77777777, &aips3->mprot0);
172 writel(0x77777777, &aips3->mprot1);
175 * Set all OPACRx to be non-bufferable, not require
176 * supervisor privilege level for access,allow for
177 * write access and untrusted master access.
179 writel(0x00000000, &aips3->opacr0);
180 writel(0x00000000, &aips3->opacr1);
181 writel(0x00000000, &aips3->opacr2);
182 writel(0x00000000, &aips3->opacr3);
183 writel(0x00000000, &aips3->opacr4);
187 static void clear_ldo_ramp(void)
189 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
192 /* ROM may modify LDO ramp up time according to fuse setting, so in
193 * order to be in the safe side we neeed to reset these settings to
194 * match the reset value: 0'b00
196 reg = readl(&anatop->ana_misc2);
197 reg &= ~(0x3f << 24);
198 writel(reg, &anatop->ana_misc2);
202 * Set the PMU_REG_CORE register
204 * Set LDO_SOC/PU/ARM regulators to the specified millivolt level.
205 * Possible values are from 0.725V to 1.450V in steps of
208 static int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
210 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
211 u32 val, step, old, reg = readl(&anatop->reg_core);
215 val = 0x00; /* Power gated off */
217 val = 0x1F; /* Power FET switched full on. No regulation */
219 val = (mv - 700) / 25;
237 old = (reg & (0x1F << shift)) >> shift;
238 step = abs(val - old);
242 reg = (reg & ~(0x1F << shift)) | (val << shift);
243 writel(reg, &anatop->reg_core);
246 * The LDO ramp-up is based on 64 clock cycles of 24 MHz = 2.6 us per
254 static u32 __data thermal_calib;
256 #define FACTOR0 10000000
257 #define FACTOR1 15976
258 #define FACTOR2 4297157
260 int raw_to_celsius(unsigned int raw, unsigned int raw_25c, unsigned int raw_hot,
261 unsigned int hot_temp)
265 if (raw_hot != 0 && hot_temp != 0) {
266 unsigned int raw_n40c, ratio;
268 ratio = ((raw_25c - raw_hot) * 100) / (hot_temp - 25);
269 raw_n40c = raw_25c + (13 * ratio) / 20;
271 temperature = (raw_n40c - raw) * 100 / ratio - 40;
273 temperature = TEMPERATURE_MIN;
275 u64 temp64 = FACTOR0;
278 * Derived from linear interpolation:
279 * slope = 0.4297157 - (0.0015976 * 25C fuse)
280 * slope = (FACTOR2 - FACTOR1 * n1) / FACTOR0
281 * (Nmeas - n1) / (Tmeas - t1) = slope
282 * We want to reduce this down to the minimum computation necessary
283 * for each temperature read. Also, we want Tmeas in millicelsius
284 * and we don't want to lose precision from integer division. So...
285 * Tmeas = (Nmeas - n1) / slope + t1
286 * milli_Tmeas = 1000 * (Nmeas - n1) / slope + 1000 * t1
287 * milli_Tmeas = -1000 * (n1 - Nmeas) / slope + 1000 * t1
288 * Let constant c1 = (-1000 / slope)
289 * milli_Tmeas = (n1 - Nmeas) * c1 + 1000 * t1
290 * Let constant c2 = n1 *c1 + 1000 * t1
291 * milli_Tmeas = c2 - Nmeas * c1
294 do_div(temp64, FACTOR1 * raw_25c - FACTOR2);
296 c2 = raw_25c * c1 + 1000 * 25;
297 temperature = (c2 - raw * c1) / 1000;
302 int read_cpu_temperature(void)
304 unsigned int reg, tmp, i;
305 unsigned int raw_25c, raw_hot, hot_temp;
307 struct anatop_regs *const anatop = (void *)ANATOP_BASE_ADDR;
308 struct mx6_ocotp_regs *const ocotp_regs = (void *)OCOTP_BASE_ADDR;
310 if (!thermal_calib) {
312 writel(1, &ocotp_regs->hw_ocotp_read_ctrl);
313 thermal_calib = readl(&ocotp_regs->hw_ocotp_ana1);
314 writel(0, &ocotp_regs->hw_ocotp_read_ctrl);
318 if (thermal_calib == 0 || thermal_calib == 0xffffffff)
319 return TEMPERATURE_MIN;
322 * [31:20] sensor value @ 25C
323 * [19:8] sensor value of hot
324 * [7:0] hot temperature value */
325 raw_25c = thermal_calib >> 20;
326 raw_hot = (thermal_calib & 0xfff00) >> 8;
327 hot_temp = thermal_calib & 0xff;
329 /* now we only using single measure, every time we measure
330 * the temperature, we will power on/off the anadig module
332 writel(BM_ANADIG_TEMPSENSE0_POWER_DOWN, &anatop->tempsense0_clr);
333 writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_set);
335 /* write measure freq */
336 writel(327, &anatop->tempsense1);
337 writel(BM_ANADIG_TEMPSENSE0_MEASURE_TEMP, &anatop->tempsense0_clr);
338 writel(BM_ANADIG_TEMPSENSE0_FINISHED, &anatop->tempsense0_clr);
339 writel(BM_ANADIG_TEMPSENSE0_MEASURE_TEMP, &anatop->tempsense0_set);
341 /* average the temperature value over multiple readings */
342 for (i = 0; i < TEMP_AVG_COUNT; i++) {
346 while ((readl(&anatop->tempsense0) &
347 BM_ANADIG_TEMPSENSE0_FINISHED) == 0) {
352 if ((readl(&anatop->tempsense0) &
353 BM_ANADIG_TEMPSENSE0_FINISHED) == 0) {
355 printf("Failed to read temp sensor\n");
361 reg = (readl(&anatop->tempsense0) &
362 BM_ANADIG_TEMPSENSE0_TEMP_VALUE) >>
363 BP_ANADIG_TEMPSENSE0_TEMP_VALUE;
367 tmp = (tmp * i + reg) / (i + 1);
368 writel(BM_ANADIG_TEMPSENSE0_FINISHED,
369 &anatop->tempsense0_clr);
372 temperature = raw_to_celsius(tmp, raw_25c, raw_hot, hot_temp);
374 /* power down anatop thermal sensor */
375 writel(BM_ANADIG_TEMPSENSE0_POWER_DOWN, &anatop->tempsense0_set);
376 writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_clr);
381 int check_cpu_temperature(int boot)
383 static int __data max_temp;
384 int boot_limit = getenv_ulong("max_boot_temp", 10, TEMPERATURE_HOT);
385 int tmp = read_cpu_temperature();
388 if (tmp < TEMPERATURE_MIN || tmp > TEMPERATURE_MAX) {
389 printf("Temperature: can't get valid data!\n");
394 if (tmp > boot_limit) {
395 printf("CPU is %d C, too hot, resetting...\n", tmp);
399 if (tmp > max_temp) {
400 if (tmp > boot_limit - TEMP_WARN_THRESHOLD)
401 printf("WARNING: CPU temperature %d C\n", tmp);
405 printf("Temperature: %d C, calibration data 0x%x\n",
407 while (tmp >= boot_limit) {
409 printf("CPU is %d C, too hot to boot, waiting...\n",
416 tmp = read_cpu_temperature();
417 if (tmp > boot_limit - TEMP_WARN_THRESHOLD && tmp != max_temp)
418 printf("WARNING: CPU temperature %d C\n", tmp);
425 static void imx_set_wdog_powerdown(bool enable)
427 struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
428 struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
430 /* Write to the PDE (Power Down Enable) bit */
431 writew(enable, &wdog1->wmcr);
432 writew(enable, &wdog2->wmcr);
435 static void set_ahb_rate(u32 val)
437 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
440 div = get_periph_clk() / val - 1;
441 reg = readl(&mxc_ccm->cbcdr);
443 writel((reg & (~MXC_CCM_CBCDR_AHB_PODF_MASK)) |
444 (div << MXC_CCM_CBCDR_AHB_PODF_OFFSET), &mxc_ccm->cbcdr);
447 static void clear_mmdc_ch_mask(void)
449 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
451 /* Clear MMDC channel mask */
452 writel(0, &mxc_ccm->ccdr);
456 static void set_preclk_from_osc(void)
458 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
461 reg = readl(&mxc_ccm->cscmr1);
462 reg |= MXC_CCM_CSCMR1_PER_CLK_SEL_MASK;
463 writel(reg, &mxc_ccm->cscmr1);
467 int arch_cpu_init(void)
471 /* Need to clear MMDC_CHx_MASK to make warm reset work. */
472 clear_mmdc_ch_mask();
475 * When low freq boot is enabled, ROM will not set AHB
476 * freq, so we need to ensure AHB freq is 132MHz in such
479 if (mxc_get_clock(MXC_ARM_CLK) == 396000000)
480 set_ahb_rate(132000000);
482 /* Set perclk to source from OSC 24MHz */
483 #if defined(CONFIG_MX6SL)
484 set_preclk_from_osc();
487 imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
489 #ifdef CONFIG_VIDEO_IPUV3
490 gd->arch.ipu_hw_rev = IPUV3_HW_REV_IPUV3H;
492 #ifdef CONFIG_APBH_DMA
493 /* Timer is required for Initializing APBH DMA */
501 int board_postclk_init(void)
503 set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */
508 #ifndef CONFIG_SYS_DCACHE_OFF
509 void enable_caches(void)
511 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
512 enum dcache_option option = DCACHE_WRITETHROUGH;
514 enum dcache_option option = DCACHE_WRITEBACK;
517 /* Avoid random hang when download by usb */
518 invalidate_dcache_all();
520 /* Enable D-cache. I-cache is already enabled in start.S */
523 /* Enable caching on OCRAM and ROM */
524 mmu_set_region_dcache_behaviour(ROMCP_ARB_BASE_ADDR,
527 mmu_set_region_dcache_behaviour(IRAM_BASE_ADDR,
533 #if defined(CONFIG_FEC_MXC)
534 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
536 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
537 struct fuse_bank *bank = &ocotp->bank[4];
538 struct fuse_bank4_regs *fuse =
539 (struct fuse_bank4_regs *)bank->fuse_regs;
541 u32 value = readl(&fuse->mac_addr_high);
542 mac[0] = (value >> 8);
545 value = readl(&fuse->mac_addr_low);
546 mac[2] = value >> 24;
547 mac[3] = value >> 16;
553 void boot_mode_apply(unsigned cfg_val)
556 struct src *psrc = (struct src *)SRC_BASE_ADDR;
557 writel(cfg_val, &psrc->gpr9);
558 reg = readl(&psrc->gpr10);
563 writel(reg, &psrc->gpr10);
566 * cfg_val will be used for
567 * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
568 * After reset, if GPR10[28] is 1, ROM will use GPR9[25:0]
569 * instead of SBMR1 to determine the boot device.
571 const struct boot_mode soc_boot_modes[] = {
572 {"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
573 /* reserved value should start rom usb */
574 {"usb", MAKE_CFGVAL(0x01, 0x00, 0x00, 0x00)},
575 {"sata", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
576 {"ecspi1:0", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)},
577 {"ecspi1:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)},
578 {"ecspi1:2", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)},
579 {"ecspi1:3", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)},
580 /* 4 bit bus width */
581 {"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
582 {"esdhc2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
583 {"esdhc3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
584 {"esdhc4", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
590 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
591 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
594 u32 reg, periph1, periph2;
596 if (is_cpu_type(MXC_CPU_MX6SX))
599 /* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
600 * to make sure PFD is working right, otherwise, PFDs may
601 * not output clock after reset, MX6DL and MX6SL have added 396M pfd
602 * workaround in ROM code, as bus clock need it
605 mask480 = ANATOP_PFD_CLKGATE_MASK(0) |
606 ANATOP_PFD_CLKGATE_MASK(1) |
607 ANATOP_PFD_CLKGATE_MASK(2) |
608 ANATOP_PFD_CLKGATE_MASK(3);
609 mask528 = ANATOP_PFD_CLKGATE_MASK(1) |
610 ANATOP_PFD_CLKGATE_MASK(3);
612 reg = readl(&ccm->cbcmr);
613 periph2 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK)
614 >> MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET);
615 periph1 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)
616 >> MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET);
618 /* Checking if PLL2 PFD0 or PLL2 PFD2 is using for periph clock */
619 if ((periph2 != 0x2) && (periph1 != 0x2))
620 mask528 |= ANATOP_PFD_CLKGATE_MASK(0);
622 if ((periph2 != 0x1) && (periph1 != 0x1) &&
623 (periph2 != 0x3) && (periph1 != 0x3))
624 mask528 |= ANATOP_PFD_CLKGATE_MASK(2);
626 writel(mask480, &anatop->pfd_480_set);
627 writel(mask528, &anatop->pfd_528_set);
628 writel(mask480, &anatop->pfd_480_clr);
629 writel(mask528, &anatop->pfd_528_clr);
632 #ifdef CONFIG_IMX_HDMI
633 void imx_enable_hdmi_phy(void)
635 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
637 reg = readb(&hdmi->phy_conf0);
638 reg |= HDMI_PHY_CONF0_PDZ_MASK;
639 writeb(reg, &hdmi->phy_conf0);
641 reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
642 writeb(reg, &hdmi->phy_conf0);
644 reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
645 writeb(reg, &hdmi->phy_conf0);
646 writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
649 void imx_setup_hdmi(void)
651 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
652 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
655 /* Turn on HDMI PHY clock */
656 reg = readl(&mxc_ccm->CCGR2);
657 reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK|
658 MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
659 writel(reg, &mxc_ccm->CCGR2);
660 writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
661 reg = readl(&mxc_ccm->chsccdr);
662 reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK|
663 MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK|
664 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
665 reg |= (CHSCCDR_PODF_DIVIDE_BY_3
666 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
667 |(CHSCCDR_IPU_PRE_CLK_540M_PFD
668 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
669 writel(reg, &mxc_ccm->chsccdr);
673 #ifndef CONFIG_SYS_L2CACHE_OFF
674 #define IOMUXC_GPR11_L2CACHE_AS_OCRAM 0x00000002
675 void v7_outer_cache_enable(void)
677 struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
680 #if defined CONFIG_MX6SL
681 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
682 val = readl(&iomux->gpr[11]);
683 if (val & IOMUXC_GPR11_L2CACHE_AS_OCRAM) {
684 /* L2 cache configured as OCRAM, reset it */
685 val &= ~IOMUXC_GPR11_L2CACHE_AS_OCRAM;
686 writel(val, &iomux->gpr[11]);
690 /* Must disable the L2 before changing the latency parameters */
691 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
693 writel(0x132, &pl310->pl310_tag_latency_ctrl);
694 writel(0x132, &pl310->pl310_data_latency_ctrl);
696 val = readl(&pl310->pl310_prefetch_ctrl);
698 /* Turn on the L2 I/D prefetch */
702 * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0
703 * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2
704 * But according to ARM PL310 errata: 752271
705 * ID: 752271: Double linefill feature can cause data corruption
706 * Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2
707 * Workaround: The only workaround to this erratum is to disable the
708 * double linefill feature. This is the default behavior.
714 writel(val, &pl310->pl310_prefetch_ctrl);
716 val = readl(&pl310->pl310_power_ctrl);
717 val |= L2X0_DYNAMIC_CLK_GATING_EN;
718 val |= L2X0_STNDBY_MODE_EN;
719 writel(val, &pl310->pl310_power_ctrl);
721 setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
724 void v7_outer_cache_disable(void)
726 struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
728 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
730 #endif /* !CONFIG_SYS_L2CACHE_OFF */